Lines Matching defs:SRA
1605 if (Opc == ISD::SRA)
1900 case ISD::SRA: return visitSRA(N);
2056 case ISD::SRA:
2485 if ((BinOpcode == ISD::SHL || BinOpcode == ISD::SRA ||
2650 SDValue NewShift = DAG.getNode(IsAdd ? ISD::SRA : ISD::SRL, DL, VT,
3924 if (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL) {
3927 auto NewSh = N1->getOpcode() == ISD::SRA ? ISD::SRL : ISD::SRA;
4175 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
4176 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
4922 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
4931 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Add, C1);
5207 ISD::SRA, DL, VT, N0,
5344 return DAG.getNode(ISD::SRA, DL, VT, X,
5974 // For binops SHL/SRL/SRA/AND:
5977 HandOpcode == ISD::SRA || HandOpcode == ISD::AND) &&
7018 ShiftOpcode == ISD::SRA))
9122 if ((WideVal.getOpcode() == ISD::SRL || WideVal.getOpcode() == ISD::SRA) &&
9721 SDValue S = N0Opcode == ISD::SRA ? N0 : N1;
9722 if (A.getOpcode() == ISD::ADD && S.getOpcode() == ISD::SRA) {
9904 BinOpLHSVal.getOpcode() == ISD::SRA ||
10181 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) {
10241 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) &&
10345 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
10346 "SRL or SRA node is required here!");
10374 if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) {
10449 bool IsSigned = N->getOpcode() == ISD::SRA;
10500 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRA, DL, VT, {N0, N1}))
10521 if (N0.getOpcode() == ISD::SRA) {
10547 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0), ShiftValue);
10637 return DAG.getNode(ISD::SRA, DL, VT, N0, NewOp1);
10646 N0.getOperand(0).getOpcode() == ISD::SRA) &&
10658 SDValue SRA =
10659 DAG.getNode(ISD::SRA, DL, LargeVT, N0Op0.getOperand(0), Amt);
10660 return DAG.getNode(ISD::TRUNCATE, DL, VT, SRA);
10843 if (N0.getOpcode() == ISD::SRA)
11463 if (Opcode != ISD::SRA && Opcode != ISD::SRL)
11472 case ISD::SRA:
11571 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC);
11577 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, X, ShAmtC);
11790 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt);
11798 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt);
11809 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt);
12663 ISD::SRA, DL, VT, LHS,
12872 if (hasOperation(ISD::SRA, VT))
13724 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SRA : ISD::SRL;
14742 } else if (Opc == ISD::SRL || Opc == ISD::SRA) {
14743 // Another special-case: SRL/SRA is basically zero/sign-extending a narrower
14759 // Attempt to fold away the SRL by using ZEXTLOAD and SRA by using SEXTLOAD.
15048 // We can turn this into an SRA iff the input to the SRL is already sign
15052 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0),
16080 // We currently avoid folding freeze over SRA/SRL, due to the problems seen
16081 // with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for
16083 if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)
22946 // TODO: support ISD::SRA
28032 SDValue Shift = DAG.getNode(ISD::SRA, DL, XType, N0, ShiftAmt);
28252 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
28347 ISD::SRA, DL, CmpOpVT, N0,