Lines Matching defs:N00
1212 SDValue N00 = N0.getOperand(0);
1226 return DAG.getNode(Opc, DL, VT, N00, OpNode, NewFlags);
1233 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, NewFlags);
1240 // (N00 & N01) & N00 --> N00 & N01
1241 // (N00 & N01) & N01 --> N00 & N01
1242 // (N00 | N01) | N00 --> N00 | N01
1243 // (N00 | N01) | N01 --> N00 | N01
1244 if (N1 == N00 || N1 == N01)
1248 // (N00 ^ N01) ^ N00 --> N01
1249 if (N1 == N00)
1251 // (N00 ^ N01) ^ N01 --> N00
1253 return N00;
1258 // Reassociate if (op N00, N1) already exist
1259 if (SDNode *NE = DAG.getNodeIfExists(Opc, DAG.getVTList(VT), {N00, N1})) {
1260 // if Op (Op N00, N1), N01 already exist
1267 if (N1 != N00) {
1270 // if Op (Op N01, N1), N00 already exist
1272 if (!DAG.doesNodeExist(Opc, DAG.getVTList(VT), {SDValue(NE, 0), N00}))
1273 return DAG.getNode(Opc, DL, VT, SDValue(NE, 0), N00);
1277 // Reassociate the operands from (OR/AND (OR/AND(N00, N001)), N1) to (OR/AND
1278 // (OR/AND(N00, N1)), N01) when N00 and N1 are comparisons with the same
1279 // predicate or to (OR/AND (OR/AND(N1, N01)), N00) when N01 and N1 are
1285 if (N1->getOpcode() == ISD::SETCC && N00->getOpcode() == ISD::SETCC &&
1288 ISD::CondCode CC00 = cast<CondCodeSDNode>(N00.getOperand(2))->get();
1291 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, Flags);
1296 return DAG.getNode(Opc, DL, VT, OpNode, N00, Flags);
2706 SDValue N00 = N0.getOperand(0);
2714 if (SDValue Add = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N1, N00}))
4022 SDValue N00 = N0.getOperand(0);
4023 if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N00, N1}))
5704 SDValue N00, N01, N02, N03;
5709 N00 = N02 = N0.getOperand(0);
5714 N00 = N0.getOperand(0);
5724 N00 = N0.getOperand(0).getOperand(0);
5734 unsigned Opcode1 = isSignedMinMax(N00, N01, N02, N03, N0CC);
7584 SDValue N00 = N0->getOperand(0);
7585 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
7586 if (!N00->hasOneUse())
7588 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
7591 N00 = N00.getOperand(0);
7609 if (N00 != N10)
7634 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
7830 SDValue N00 = N0.getOperand(0);
7832 if (!(isBSwapHWordElement(N01, Parts) && isBSwapHWordPair(N00, Parts)) &&
7833 !(isBSwapHWordElement(N00, Parts) && isBSwapHWordPair(N01, Parts)))
7927 SDValue N00 = N0Resized.getOperand(0);
7931 if (N00 == N1Resized || N01 == N1Resized)
7936 if (SDValue NotOperand = getBitwiseNotOperand(N01, N00,
7939 return DAG.getNode(ISD::OR, DL, VT, DAG.getZExtOrTrunc(N00, DL, VT),
7944 if (SDValue NotOperand = getBitwiseNotOperand(N00, N01,
9672 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1);
9673 if (isOneUseSetCC(N01) || isOneUseSetCC(N00)) {
9675 N00 = DAG.getNode(ISD::XOR, SDLoc(N00), VT, N00, N1); // N00 = ~N00
9677 AddToWorklist(N00.getNode()); AddToWorklist(N01.getNode());
9678 return DAG.getNode(NewOpcode, DL, VT, N00, N01);
9685 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1);
9686 if (isa<ConstantSDNode>(N01) || isa<ConstantSDNode>(N00)) {
9688 N00 = DAG.getNode(ISD::XOR, SDLoc(N00), VT, N00, N1); // N00 = ~N00
9690 AddToWorklist(N00.getNode()); AddToWorklist(N01.getNode());
9691 return DAG.getNode(NewOpcode, DL, VT, N00, N01);
9933 // (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC)
9940 SDValue N00 = N->getOperand(0).getOperand(0);
9941 SDValue Trunc00 = DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N00);
10057 SDValue N00 = N0->getOperand(0);
10061 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
10062 TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
10066 return DAG.getNode(ISD::AND, DL, VT, N00, C);
13736 SDValue N00 = N0.getOperand(0);
13740 EVT N00VT = N00.getValueType();
13762 return DAG.getSetCC(DL, VT, N00, N01, CC);
13769 SDValue VsetCC = DAG.getSetCC(DL, MatchingVecType, N00, N01, CC);
13812 if (IsFreeToExtend(N00) && IsFreeToExtend(N01)) {
13813 SDValue Ext0 = DAG.getNode(ExtOpcode, DL, VT, N00);
13836 if (SDValue SCC = SimplifySelectCC(DL, N00, N01, ExtTrueVal, Zero, CC, true))
13847 SDValue SetCC = DAG.getSetCC(DL, SetCCVT, N00, N01, CC);
13885 SDValue N00 = N0.getOperand(0);
13887 if ((N00.getOpcode() == ISD::TRUNCATE || TLI.isTruncateFree(N00, ExtVT)) &&
13889 SDValue T = DAG.getNode(ISD::TRUNCATE, DL, ExtVT, N00);
14993 SDValue N00 = N0.getOperand(0);
14994 unsigned N00Bits = N00.getScalarValueSizeInBits();
14996 DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits) &&
14998 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N00);
15005 SDValue N00 = N0.getOperand(0);
15006 unsigned N00Bits = N00.getScalarValueSizeInBits();
15008 unsigned SrcElts = N00.getValueType().getVectorMinNumElements();
15013 DAG.ComputeMaxSignificantBits(N00) <= ExtVTBits))) &&
15016 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, N00);
15022 SDValue N00 = N0.getOperand(0);
15023 if (N00.getScalarValueSizeInBits() == ExtVTBits &&
15025 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N00);
15615 SDValue N00 = N0.getOperand(0);
15616 if (N00.getOpcode() == ISD::SIGN_EXTEND ||
15617 N00.getOpcode() == ISD::ZERO_EXTEND ||
15618 N00.getOpcode() == ISD::ANY_EXTEND) {
15619 if (N00.getOperand(0)->getValueType(0).getVectorElementType() ==
15622 N00.getOperand(0), N0.getOperand(1));
16415 SDValue N00 = N0.getOperand(0);
16416 if (isContractableFMUL(N00) &&
16418 N00.getValueType())) {
16421 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)),
16422 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)), N1);
16482 SDValue N00 = N0.getOperand(0);
16483 if (isFusedOp(N00)) {
16484 SDValue N002 = N00.getOperand(2);
16487 N00.getValueType())) {
16488 return FoldFAddFPExtFMAFMul(N00.getOperand(0), N00.getOperand(1),
16628 SDValue N00 = N0.getOperand(0).getOperand(0);
16631 matcher.getNode(ISD::FNEG, SL, VT, N00), N01,
16640 SDValue N00 = N0.getOperand(0);
16641 if (isContractableFMUL(N00) &&
16643 N00.getValueType())) {
16646 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)),
16647 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)),
16676 SDValue N00 = N0.getOperand(0);
16677 if (matcher.match(N00, ISD::FNEG)) {
16678 SDValue N000 = N00.getOperand(0);
16681 N00.getValueType())) {
16700 SDValue N00 = N0.getOperand(0);
16701 if (matcher.match(N00, ISD::FP_EXTEND)) {
16702 SDValue N000 = N00.getOperand(0);
16788 SDValue N00 = N0.getOperand(0);
16789 if (isFusedOp(N00)) {
16790 SDValue N002 = N00.getOperand(2);
16793 N00.getValueType())) {
16796 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(0)),
16797 matcher.getNode(ISD::FP_EXTEND, SL, VT, N00.getOperand(1)),
17407 SDValue N00 = N0.getOperand(0);
17409 // Avoid an infinite loop by making sure that N00 is not a constant
17412 !DAG.isConstantFPBuildVectorOrConstantFP(N00)) {
17414 return DAG.getNode(ISD::FMUL, DL, VT, N00, MulConsts);
25907 SDValue N00 = N0.getOperand(0);
25911 unsigned ExtSrcSizeInBits = N00.getScalarValueSizeInBits();
25941 return DAG.getBitcast(VT, N00);