Lines Matching defs:N0
430 SDValue visitADDLikeCommutative(SDValue N0, SDValue N1, SDNode *LocReference);
436 SDValue visitUADDOLike(SDValue N0, SDValue N1, SDNode *N);
442 SDValue visitUADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
444 SDValue visitSADDO_CARRYLike(SDValue N0, SDValue N1, SDValue CarryIn,
453 SDValue visitSDIVLike(SDValue N0, SDValue N1, SDNode *N);
455 SDValue visitUDIVLike(SDValue N0, SDValue N1, SDNode *N);
466 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
468 SDValue visitORLike(SDValue N0, SDValue N1, const SDLoc &DL);
582 SDValue N0,
584 SDValue reassociateOpsCommutative(unsigned Opc, const SDLoc &DL, SDValue N0,
586 SDValue reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
589 EVT VT, SDValue N0, SDValue N1,
599 SDValue SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2);
600 SDValue SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
604 const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
607 SDValue foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0, SDValue N1,
611 SDValue foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
619 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
648 SDValue buildOptimizedSREM(SDValue N0, SDValue N1, SDNode *N);
661 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
663 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
668 SDValue MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos, SDValue Neg,
1014 SDValue N0, N1, N2;
1015 if (isSetCCEquivalent(N, N0, N1, N2) && N->hasOneUse())
1086 SDValue N0,
1097 if (N0.getOpcode() != ISD::ADD)
1145 if (auto *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1146 if (N0.hasOneUse())
1176 if (auto *GA = dyn_cast<GlobalAddressSDNode>(N0.getOperand(1)))
1202 /// Helper for DAGCombiner::reassociateOps. Try to reassociate (Opc N0, N1) if
1203 /// \p N0 is the same kind of operation as \p Opc.
1205 SDValue N0, SDValue N1,
1207 EVT VT = N0.getValueType();
1209 if (N0.getOpcode() != Opc)
1212 SDValue N00 = N0.getOperand(0);
1213 SDValue N01 = N0.getOperand(1);
1217 if (N0.getOpcode() == ISD::ADD && N0->getFlags().hasNoUnsignedWrap() &&
1225 N0->getFlags().hasDisjoint());
1230 if (TLI.isReassocProfitable(DAG, N0, N1)) {
1233 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, NewFlags);
1245 return N0;
1256 if (TLI.isReassocProfitable(DAG, N0, N1)) {
1291 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N00, N1, Flags);
1295 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N01, N1, Flags);
1305 /// Try to reassociate commutative (Opc N0, N1) if either \p N0 or \p N1 is the
1307 SDValue DAGCombiner::reassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
1312 if (N0.getValueType().isFloatingPoint() ||
1317 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N0, N1, Flags))
1319 if (SDValue Combined = reassociateOpsCommutative(Opc, DL, N1, N0, Flags))
1328 const SDLoc &DL, EVT VT, SDValue N0,
1330 if (N0.getOpcode() == RedOpc && N1.getOpcode() == RedOpc &&
1331 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
1332 N0->hasOneUse() && N1->hasOneUse() &&
1333 TLI.isOperationLegalOrCustom(Opc, N0.getOperand(0).getValueType()) &&
1334 TLI.shouldReassociateReduction(RedOpc, N0.getOperand(0).getValueType())) {
1337 DAG.getNode(Opc, DL, N0.getOperand(0).getValueType(),
1338 N0.getOperand(0), N1.getOperand(0)));
1536 SDValue N0 = Op.getOperand(0);
1537 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1547 // We are always replacing N0/N1's use in N and only need additional
1552 Replace0 &= !N0->hasOneUse();
1553 Replace1 &= (N0 != N1) && !N1->hasOneUse();
1560 if (Replace0 && Replace1 && N0->isPredecessorOf(N1.getNode())) {
1561 std::swap(N0, N1);
1567 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1604 SDValue N0 = Op.getOperand(0);
1606 N0 = SExtPromoteOperand(N0, PVT);
1608 N0 = ZExtPromoteOperand(N0, PVT);
1610 N0 = PromoteOperand(N0, PVT, Replace);
1612 if (!N0.getNode())
1618 DAG.getNode(ISD::TRUNCATE, DL, VT, DAG.getNode(Opc, DL, PVT, N0, N1));
1621 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
2075 SDValue N0 = N->getOperand(0);
2079 if (N0 != N1 && (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1))) {
2080 SDValue Ops[] = {N1, N0};
2421 SDValue N0 = N->getOperand(0);
2424 std::swap(N0, N1);
2441 // This transform increases uses of N0, so freeze it to be safe.
2442 // binop N0, (vselect Cond, IDC, FVal) --> vselect Cond, N0, (binop N0, FVal)
2445 SDValue F0 = DAG.getFreeze(N0);
2449 // binop N0, (vselect Cond, TVal, IDC) --> vselect Cond, (binop N0, TVal), N0
2451 SDValue F0 = DAG.getFreeze(N0);
2599 SDValue N0 = N->getOperand(0);
2600 EVT VT = N0.getValueType();
2668 SDValue N0 = N->getOperand(0);
2670 EVT VT = N0.getValueType();
2674 if (N0.isUndef())
2675 return N0;
2680 if (SDValue C = DAG.FoldConstantArithmetic(ISD::ADD, DL, VT, {N0, N1}))
2684 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
2686 return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
2688 if (areBitwiseNotOfEachother(N0, N1))
2698 return N0;
2703 return N0;
2705 if (N0.getOpcode() == ISD::SUB) {
2706 SDValue N00 = N0.getOperand(0);
2707 SDValue N01 = N0.getOperand(1);
2711 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Sub);
2715 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
2722 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() &&
2724 SDValue X = N0.getOperand(0);
2738 if (DAG.isADDLike(N0)) {
2739 SDValue N01 = N0.getOperand(1);
2741 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), Add);
2748 if (!reassociationCanBreakAddressingModePattern(ISD::ADD, DL, N, N0, N1)) {
2749 if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
2758 auto ReassociateAddOr = [&](SDValue N0, SDValue N1) {
2759 if (DAG.isADDLike(N0) && N0.hasOneUse() &&
2760 isConstantOrConstantVector(N0.getOperand(1), /* NoOpaque */ true)) {
2761 // If N0's type does not split or is a sign mask, it does not introduce
2763 auto TyActn = TLI.getTypeAction(*DAG.getContext(), N0.getValueType());
2766 isMinSignedConstant(N0.getOperand(1));
2770 DAG.getNode(ISD::ADD, DL, VT, N1, N0.getOperand(0)),
2771 N0.getOperand(1));
2775 if (SDValue Add = ReassociateAddOr(N0, N1))
2777 if (SDValue Add = ReassociateAddOr(N1, N0))
2782 reassociateReduction(ISD::VECREDUCE_ADD, ISD::ADD, DL, VT, N0, N1))
2789 if (sd_match(N0, m_Neg(m_Value(A))))
2794 return DAG.getNode(ISD::SUB, DL, VT, N0, B);
2797 if (sd_match(N1, m_Sub(m_Value(B), m_Specific(N0))))
2801 if (sd_match(N0, m_Sub(m_Value(B), m_Specific(N1))))
2805 if (sd_match(N0, m_Sub(m_Value(A), m_Value(B))) &&
2810 if (sd_match(N0, m_Sub(m_Value(A), m_Value(B))) &&
2816 if (sd_match(N1, m_Sub(m_Value(B), m_Add(m_Specific(N0), m_Value(C)))))
2821 m_AnyOf(m_Add(m_Sub(m_Value(B), m_Specific(N0)), m_Value(C)),
2822 m_Sub(m_Sub(m_Value(B), m_Specific(N0)), m_Value(C)))))
2826 if (sd_match(N0, m_OneUse(m_Sub(m_Value(A), m_Value(B)))) &&
2830 DAG.getNode(ISD::ADD, SDLoc(N0), VT, A, C),
2834 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
2839 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchUSUBSAT,
2841 return DAG.getNode(ISD::USUBSAT, DL, VT, N0.getOperand(0),
2842 N0.getOperand(1));
2850 if (isBitwiseNot(N0))
2852 N0.getOperand(0));
2855 if (N0.getOpcode() == ISD::ADD) {
2858 if (isBitwiseNot(N0.getOperand(0))) {
2859 A = N0.getOperand(1);
2860 Xor = N0.getOperand(0);
2861 } else if (isBitwiseNot(N0.getOperand(1))) {
2862 A = N0.getOperand(0);
2863 Xor = N0.getOperand(1);
2874 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD &&
2875 N0.hasOneUse() &&
2879 SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT);
2880 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(1), Not);
2885 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
2887 SDValue Not = DAG.getNOT(DL, N0.getOperand(1), VT);
2888 return DAG.getNode(ISD::ADD, DL, VT, Not, N0.getOperand(0));
2896 if (sd_match(N0, m_OneUse(m_Mul(m_Add(m_Value(A), m_ConstInt(CA)),
2904 N0->getFlags().hasNoUnsignedWrap() &&
2905 N0.getOperand(0)->getFlags().hasNoUnsignedWrap()) {
2908 N0->getFlags().hasNoSignedWrap() &&
2909 N0.getOperand(0)->getFlags().hasNoSignedWrap())
2919 if (sd_match(N0, m_OneUse(m_Add(
2929 N0.getOperand(0) == B ? N0.getOperand(1) : N0.getOperand(0);
2931 N0->getFlags().hasNoUnsignedWrap() &&
2936 N0->getFlags().hasNoSignedWrap() &&
2951 if (SDValue Combined = visitADDLikeCommutative(N0, N1, N))
2954 if (SDValue Combined = visitADDLikeCommutative(N1, N0, N))
2962 SDValue N0 = N->getOperand(0);
2963 EVT VT = N0.getValueType();
2981 SDValue N0 = N->getOperand(0);
2983 EVT VT = N0.getValueType();
3001 DAG.haveNoCommonBitsSet(N0, N1))
3002 return DAG.getNode(ISD::OR, DL, VT, N0, N1, SDNodeFlags::Disjoint);
3005 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) {
3006 const APInt &C0 = N0->getConstantOperandAPInt(0);
3012 if (N0.getOpcode() == ISD::ADD &&
3013 N0.getOperand(1).getOpcode() == ISD::VSCALE &&
3015 const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
3018 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), VS);
3022 if (N0.getOpcode() == ISD::STEP_VECTOR &&
3024 const APInt &C0 = N0->getConstantOperandAPInt(0);
3031 if (N0.getOpcode() == ISD::ADD &&
3032 N0.getOperand(1).getOpcode() == ISD::STEP_VECTOR &&
3034 const APInt &SV0 = N0.getOperand(1)->getConstantOperandAPInt(0);
3038 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), SV);
3046 SDValue N0 = N->getOperand(0);
3048 EVT VT = N0.getValueType();
3053 if (N0.isUndef() || N1.isUndef())
3057 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
3061 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3063 return DAG.getNode(Opcode, DL, VT, N1, N0);
3072 return N0;
3077 return N0;
3080 if (DAG.willNotOverflowAdd(IsSigned, N0, N1))
3081 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
3138 static SDValue foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1,
3146 EVT VT = N0.getValueType();
3157 // add N0, (and (AssertSext X, i1), 1) --> sub N0, X
3158 // sub N0, (and (AssertSext X, i1), 1) --> add N0, X
3159 return DAG.getNode(IsAdd ? ISD::SUB : ISD::ADD, DL, VT, N0, N10);
3162 /// Helper for doing combines based on N0 and N1 being added to each other.
3163 SDValue DAGCombiner::visitADDLikeCommutative(SDValue N0, SDValue N1,
3165 EVT VT = N0.getValueType();
3171 return DAG.getNode(ISD::SUB, DL, VT, N0,
3174 if (SDValue V = foldAddSubMasked1(true, N0, N1, DAG, DL))
3181 if (!TLI.preferIncOfAddToSubOfNot(VT) && N0.getOpcode() == ISD::ADD &&
3182 N0.hasOneUse() && isOneOrOneSplat(N0.getOperand(1)) &&
3184 (Level >= AfterLegalizeDAG || (!N0->getFlags().hasNoUnsignedWrap() &&
3185 !N0->getFlags().hasNoSignedWrap()))) {
3186 SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT);
3190 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse()) {
3194 if (isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
3195 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), N1);
3196 return DAG.getNode(ISD::SUB, DL, VT, Add, N0.getOperand(1));
3200 if (isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
3201 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N1, N0.getOperand(1));
3202 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(0));
3207 if (N0.getOpcode() == ISD::MUL && N0.getOperand(0) == N1 &&
3208 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true) &&
3209 N0.hasOneUse()) {
3210 SDValue NewC = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1),
3212 return DAG.getNode(ISD::MUL, DL, VT, N0.getOperand(0), NewC);
3218 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
3219 N0.getOperand(0).getScalarValueSizeInBits() == 1 &&
3221 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
3231 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
3239 N0, N1.getOperand(0), N1.getOperand(2));
3245 DAG.getVTList(VT, Carry.getValueType()), N0,
3252 SDValue N0 = N->getOperand(0);
3254 EVT VT = N0.getValueType();
3259 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
3263 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3266 return DAG.getNode(ISD::ADDC, DL, N->getVTList(), N1, N0);
3270 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
3274 if (DAG.computeOverflowForUnsignedAdd(N0, N1) == SelectionDAG::OFK_Never)
3275 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
3305 SDValue N0 = N->getOperand(0);
3307 EVT VT = N0.getValueType();
3315 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
3319 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
3321 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
3325 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
3328 if (DAG.willNotOverflowAdd(IsSigned, N0, N1))
3329 return CombineTo(N, DAG.getNode(ISD::ADD, DL, VT, N0, N1),
3334 if (isBitwiseNot(N0) && isOneOrOneSplat(N1))
3336 DAG.getConstant(0, DL, VT), N0.getOperand(0));
3339 if (isBitwiseNot(N0) && isOneOrOneSplat(N1)) {
3341 DAG.getConstant(0, DL, VT), N0.getOperand(0));
3346 if (SDValue Combined = visitUADDOLike(N0, N1, N))
3349 if (SDValue Combined = visitUADDOLike(N1, N0, N))
3356 SDValue DAGCombiner::visitUADDOLike(SDValue N0, SDValue N1, SDNode *N) {
3357 EVT VT = N0.getValueType();
3367 return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), N0, Y,
3374 return DAG.getNode(ISD::UADDO_CARRY, SDLoc(N), N->getVTList(), N0,
3381 SDValue N0 = N->getOperand(0);
3386 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3390 N1, N0, CarryIn);
3394 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
3400 SDValue N0 = N->getOperand(0);
3406 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3409 return DAG.getNode(ISD::UADDO_CARRY, DL, N->getVTList(), N1, N0, CarryIn);
3415 return DAG.getNode(ISD::UADDO, DL, N->getVTList(), N0, N1);
3419 if (isNullConstant(N0) && isNullConstant(N1)) {
3420 EVT VT = N0.getValueType();
3429 if (SDValue Combined = visitUADDO_CARRYLike(N0, N1, CarryIn, N))
3432 if (SDValue Combined = visitUADDO_CARRYLike(N1, N0, CarryIn, N))
3440 SDValue Ops[] = {N1, N0, CarryIn};
3565 SDValue N0, SDValue N1, SDNode *N) {
3566 SDValue Carry0 = getAsCarry(TLI, N0);
3636 SDValue DAGCombiner::visitUADDO_CARRYLike(SDValue N0, SDValue N1,
3640 if (isBitwiseNot(N0))
3644 N0.getOperand(0), NotC);
3653 if ((N0.getOpcode() == ISD::ADD ||
3654 (N0.getOpcode() == ISD::UADDO && N0.getResNo() == 0 &&
3655 N0.getValue(1) != CarryIn)) &&
3658 N0.getOperand(0), N0.getOperand(1), CarryIn);
3667 if (auto R = combineUADDO_CARRYDiamond(*this, DAG, N0, Y, CarryIn, N))
3669 if (auto R = combineUADDO_CARRYDiamond(*this, DAG, N0, CarryIn, Y, N))
3676 SDValue DAGCombiner::visitSADDO_CARRYLike(SDValue N0, SDValue N1,
3679 if (isBitwiseNot(N0)) {
3682 N0.getOperand(0), NotC);
3689 SDValue N0 = N->getOperand(0);
3695 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3698 return DAG.getNode(ISD::SADDO_CARRY, DL, N->getVTList(), N1, N0, CarryIn);
3704 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0, N1);
3707 if (SDValue Combined = visitSADDO_CARRYLike(N0, N1, CarryIn, N))
3710 if (SDValue Combined = visitSADDO_CARRYLike(N1, N0, CarryIn, N))
3822 SDValue N0 = N->getOperand(0);
3823 EVT VT = N0.getValueType();
3877 SDValue N0 = N->getOperand(0);
3879 EVT VT = N0.getValueType();
3894 if (PeekThroughFreeze(N0) == PeekThroughFreeze(N1))
3898 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N1}))
3908 return N0;
3916 return DAG.getNode(ISD::ADD, DL, VT, N0,
3919 if (isNullOrNullSplat(N0)) {
3935 return N0;
3941 return N0;
3980 if (isAllOnesOrAllOnesSplat(N0))
3981 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
3985 return DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(1));
3988 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
3992 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
3993 return N0.getOperand(1);
3996 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
3997 return N0.getOperand(0);
4000 if (N0.getOpcode() == ISD::ADD) {
4001 SDValue N01 = N0.getOperand(1);
4003 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(0), NewC);
4009 if (SDValue NewC = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {N0, N11}))
4014 if (N0.getOpcode() == ISD::SUB) {
4015 SDValue N01 = N0.getOperand(1);
4017 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), NewC);
4021 if (N0.getOpcode() == ISD::SUB) {
4022 SDValue N00 = N0.getOperand(0);
4024 return DAG.getNode(ISD::SUB, DL, VT, NewC, N0.getOperand(1));
4030 if (sd_match(N0, m_Add(m_Value(A), m_Add(m_Specific(N1), m_Value(C)))))
4034 if (sd_match(N0, m_Add(m_Value(A), m_Sub(m_Specific(N1), m_Value(C)))))
4038 if (sd_match(N0, m_Sub(m_Value(A), m_Sub(m_Value(B), m_Specific(N1)))))
4043 return DAG.getNode(ISD::ADD, DL, VT, N0,
4047 if (sd_match(N1, m_And(m_Specific(N0), m_Value(B))) &&
4049 return DAG.getNode(ISD::AND, DL, VT, N0, DAG.getNOT(DL, B, VT));
4053 return DAG.getNode(ISD::ADD, DL, VT, N0,
4057 if (N0.isUndef())
4058 return N0;
4072 if (SDValue V = foldAddSubMasked1(false, N0, N1, DAG, DL))
4087 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, N1.getOperand(0));
4093 if (!reassociationCanBreakAddressingModePattern(ISD::SUB, DL, N, N0, N1) &&
4094 N0.getOpcode() == ISD::ADD && N0.hasOneUse() &&
4095 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
4096 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
4097 return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1));
4102 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
4107 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
4108 isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) {
4109 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
4110 return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
4113 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
4114 isConstantOrConstantVector(N0.getOperand(0), /*NoOpaques=*/true)) {
4115 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1), N1);
4116 return DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), Add);
4127 return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
4133 sd_match(N0, m_Xor(m_Specific(A), m_Specific(N1))))
4137 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
4152 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
4159 return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
4165 return DAG.getNode(ISD::ADD, DL, VT, N0,
4170 // sub N0, (lshr N10, width-1) --> add N0, (ashr N10, width-1)
4176 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
4182 // N0 - (X << BW-1) --> N0 + (X << BW-1)
4186 return DAG.getNode(ISD::ADD, DL, VT, N1, N0);
4190 if (N0.getOpcode() == ISD::USUBO_CARRY && isNullConstant(N0.getOperand(1)) &&
4191 N0.getResNo() == 0 && N0.hasOneUse())
4192 return DAG.getNode(ISD::USUBO_CARRY, DL, N0->getVTList(),
4193 N0.getOperand(0), N1, N0.getOperand(2));
4197 if (SDValue Carry = getAsCarry(TLI, N0)) {
4209 if (ConstantSDNode *C0 = isConstOrConstSplat(N0)) {
4214 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
4220 sd_match(N0, m_SMaxLike(m_Value(A), m_Value(B))) &&
4226 sd_match(N0, m_SMinLike(m_Value(A), m_Value(B))) &&
4232 sd_match(N0, m_UMaxLike(m_Value(A), m_Value(B))) &&
4238 sd_match(N0, m_UMinLike(m_Value(A), m_Value(B))) &&
4247 SDValue N0 = N->getOperand(0);
4249 EVT VT = N0.getValueType();
4254 if (N0.isUndef() || N1.isUndef())
4258 if (N0 == N1)
4262 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
4272 return N0;
4277 return N0;
4280 if (DAG.willNotOverflowSub(IsSigned, N0, N1))
4281 return DAG.getNode(ISD::SUB, DL, VT, N0, N1);
4287 SDValue N0 = N->getOperand(0);
4289 EVT VT = N0.getValueType();
4294 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
4298 if (N0 == N1)
4304 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, DL, MVT::Glue));
4307 if (isAllOnesConstant(N0))
4308 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
4315 SDValue N0 = N->getOperand(0);
4317 EVT VT = N0.getValueType();
4325 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
4329 if (N0 == N1)
4336 return DAG.getNode(ISD::SADDO, DL, N->getVTList(), N0,
4341 return CombineTo(N, N0, DAG.getConstant(0, DL, CarryVT));
4344 if (DAG.willNotOverflowSub(IsSigned, N0, N1))
4345 return CombineTo(N, DAG.getNode(ISD::SUB, DL, VT, N0, N1),
4349 if (!IsSigned && isAllOnesOrAllOnesSplat(N0))
4350 return CombineTo(N, DAG.getNode(ISD::XOR, DL, VT, N1, N0),
4357 SDValue N0 = N->getOperand(0);
4363 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
4369 SDValue N0 = N->getOperand(0);
4377 return DAG.getNode(ISD::USUBO, SDLoc(N), N->getVTList(), N0, N1);
4384 SDValue N0 = N->getOperand(0);
4392 return DAG.getNode(ISD::SSUBO, SDLoc(N), N->getVTList(), N0, N1);
4401 SDValue N0 = N->getOperand(0);
4404 EVT VT = N0.getValueType();
4407 if (N0.isUndef() || N1.isUndef())
4411 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4413 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0, Scale);
4423 SDValue N0 = N->getOperand(0);
4425 EVT VT = N0.getValueType();
4432 if (N0.isUndef() || N1.isUndef())
4436 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MUL, DL, VT, {N0, N1}))
4440 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
4442 return Matcher.getNode(ISD::MUL, DL, VT, N1, N0);
4472 return N0;
4480 return Matcher.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), N0);
4486 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
4488 return Matcher.getNode(ISD::SHL, DL, VT, N0, Trunc);
4500 Matcher.getNode(ISD::SHL, DL, VT, N0,
4511 if (SDNode *LoHi = DAG.getNodeIfExists(LoHiOpc, LoHiVT, {N0, N1}))
4514 if (SDNode *LoHi = DAG.getNodeIfExists(LoHiOpc, LoHiVT, {N1, N0}))
4558 DAG.getNode(ISD::SHL, DL, VT, N0, DAG.getConstant(ShAmt, DL, VT));
4561 DAG.getNode(ISD::SHL, DL, VT, N0,
4563 : DAG.getNode(MathOp, DL, VT, Shl, N0);
4571 if (sd_context_match(N0, Matcher, m_Opc(ISD::SHL))) {
4572 SDValue N01 = N0.getOperand(1);
4574 return DAG.getNode(ISD::MUL, DL, VT, N0.getOperand(0), C3);
4583 if (sd_context_match(N0, Matcher, m_OneUse(m_Opc(ISD::SHL))) &&
4584 isConstantOrConstantVector(N0.getOperand(1))) {
4585 Sh = N0; Y = N1;
4588 Sh = N1; Y = N0;
4598 if (sd_context_match(N0, Matcher, m_Opc(ISD::ADD)) &&
4600 DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1)) &&
4601 isMulAddWithConstProfitable(N, N0, N1))
4604 Matcher.getNode(ISD::MUL, SDLoc(N0), VT, N0.getOperand(0), N1),
4605 Matcher.getNode(ISD::MUL, SDLoc(N1), VT, N0.getOperand(1), N1));
4609 if (!UseVP && N0.getOpcode() == ISD::VSCALE && NC1) {
4610 const APInt &C0 = N0.getConstantOperandAPInt(0);
4617 if (!UseVP && N0.getOpcode() == ISD::STEP_VECTOR &&
4619 const APInt &C0 = N0.getConstantOperandAPInt(0);
4660 return DAG.getNode(ISD::AND, DL, VT, N0, DAG.getBuildVector(VT, DL, Mask));
4667 if (SDValue RMUL = reassociateOps(ISD::MUL, DL, N0, N1, N->getFlags()))
4674 reassociateReduction(ISD::VECREDUCE_MUL, ISD::MUL, DL, VT, N0, N1))
4773 SDValue N0 = N->getOperand(0);
4787 if (DAG.isUndef(Opc, {N0, N1}))
4792 if (N0.isUndef())
4797 ConstantSDNode *N0C = isConstOrConstSplat(N0);
4799 return N0;
4803 if (N0 == N1)
4813 return IsDiv ? N0 : DAG.getConstant(0, DL, VT);
4819 SDValue N0 = N->getOperand(0);
4826 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, {N0, N1}))
4837 return DAG.getNegative(N0, DL, VT);
4841 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4853 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
4854 return DAG.getNode(ISD::UDIV, DL, N1.getValueType(), N0, N1);
4856 if (SDValue V = visitSDIVLike(N0, N1, N)) {
4860 { N0, N1 })) {
4862 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
4897 SDValue DAGCombiner::visitSDIVLike(SDValue N0, SDValue N1, SDNode *N) {
4913 EVT ShiftAmtTy = getShiftAmountTy(N0.getValueType());
4922 SDValue Sign = DAG.getNode(ISD::SRA, DL, VT, N0,
4926 // Add (N0 < 0) ? abs2 - 1 : 0;
4929 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Srl);
4941 Sra = DAG.getSelect(DL, VT, IsOneOrAllOnes, N0, Sra);
4967 SDValue N0 = N->getOperand(0);
4974 if (SDValue C = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT, {N0, N1}))
4985 return DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, N0, N1, ISD::SETEQ),
4996 if (SDValue V = visitUDIVLike(N0, N1, N)) {
5000 { N0, N1 })) {
5002 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
5027 SDValue DAGCombiner::visitUDIVLike(SDValue N0, SDValue N1, SDNode *N) {
5036 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
5039 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
5055 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
5070 SDValue DAGCombiner::buildOptimizedSREM(SDValue N0, SDValue N1, SDNode *N) {
5072 !DAG.doesNodeExist(ISD::SDIV, N->getVTList(), {N0, N1})) {
5083 SDValue N0 = N->getOperand(0);
5092 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
5099 SDValue F0 = DAG.getFreeze(N0);
5113 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
5114 return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
5121 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
5132 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
5148 if (SDValue OptimizedRem = buildOptimizedSREM(N0, N1, N))
5153 isSigned ? visitSDIVLike(N0, N1, N) : visitUDIVLike(N0, N1, N);
5158 { N0, N1 }))
5161 SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, Mul);
5176 SDValue N0 = N->getOperand(0);
5182 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHS, DL, VT, {N0, N1}))
5186 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5188 return DAG.getNode(ISD::MULHS, DL, N->getVTList(), N1, N0);
5207 ISD::SRA, DL, VT, N0,
5208 DAG.getShiftAmountConstant(N0.getScalarValueSizeInBits() - 1, VT, DL));
5211 if (N0.isUndef() || N1.isUndef())
5222 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
5224 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
5235 SDValue N0 = N->getOperand(0);
5241 if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHU, DL, VT, {N0, N1}))
5245 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5247 return DAG.getNode(ISD::MULHU, DL, N->getVTList(), N1, N0);
5268 if (N0.isUndef() || N1.isUndef())
5278 EVT ShiftVT = getShiftAmountTy(N0.getValueType());
5280 return DAG.getNode(ISD::SRL, DL, VT, N0, Trunc);
5292 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
5294 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
5312 SDValue N0 = N->getOperand(0);
5319 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
5323 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5325 return DAG.getNode(Opcode, DL, N->getVTList(), N1, N0);
5332 if (N0.isUndef())
5335 return N0;
5338 if (N0 == N1 && Level >= AfterLegalizeTypes)
5339 return N0;
5374 ISD::AVGCEILU, DL, VT, N0,
5376 if (DAG.isKnownNeverZero(N0))
5379 DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getAllOnesConstant(DL, VT)));
5408 SDValue N0 = N->getOperand(0);
5414 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
5418 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5420 return DAG.getNode(Opcode, DL, N->getVTList(), N1, N0);
5427 if (N0.isUndef() || N1.isUndef())
5431 if (N0 == N1)
5447 DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1))
5448 return DAG.getNode(ISD::ABDU, DL, VT, N1, N0);
5506 SDValue N0 = N->getOperand(0);
5512 if (isa<ConstantSDNode>(N0) && isa<ConstantSDNode>(N1))
5513 return DAG.getNode(ISD::SMUL_LOHI, DL, N->getVTList(), N0, N1);
5516 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5518 return DAG.getNode(ISD::SMUL_LOHI, DL, N->getVTList(), N1, N0);
5527 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
5534 // Compute the low part as N0.
5547 SDValue N0 = N->getOperand(0);
5553 if (isa<ConstantSDNode>(N0) && isa<ConstantSDNode>(N1))
5554 return DAG.getNode(ISD::UMUL_LOHI, DL, N->getVTList(), N0, N1);
5557 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5559 return DAG.getNode(ISD::UMUL_LOHI, DL, N->getVTList(), N1, N0);
5561 // (umul_lohi N0, 0) -> (0, 0)
5567 // (umul_lohi N0, 1) -> (N0, 0)
5570 return CombineTo(N, N0, Zero);
5580 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
5587 // Compute the low part as N0.
5597 SDValue N0 = N->getOperand(0);
5599 EVT VT = N0.getValueType();
5605 ConstantSDNode *N0C = isConstOrConstSplat(N0);
5621 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5623 return DAG.getNode(N->getOpcode(), DL, N->getVTList(), N1, N0);
5635 N->getVTList(), N0, N0);
5639 SDValue And = DAG.getNode(ISD::AND, DL, VT, N0, N1);
5646 if (DAG.willNotOverflowMul(IsSigned, N0, N1))
5647 return CombineTo(N, DAG.getNode(ISD::MUL, DL, VT, N0, N1),
5657 // same as SimplifySelectCC. N0<N1 ? N2 : N3.
5658 static SDValue isSaturatingMinMax(SDValue N0, SDValue N1, SDValue N2,
5661 auto isSignedMinMax = [&](SDValue N0, SDValue N1, SDValue N2, SDValue N3,
5665 if (N0 != N2 && (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0)))
5680 unsigned Opcode0 = isSignedMinMax(N0, N1, N2, N3, CC);
5686 if (N0.getOpcode() == ISD::FP_TO_SINT && Opcode0 == ISD::SMAX) {
5688 EVT IntVT = N0.getValueType().getScalarType();
5689 EVT FPVT = N0.getOperand(0).getValueType().getScalarType();
5698 return N0;
5706 switch (N0.getOpcode()) {
5709 N00 = N02 = N0.getOperand(0);
5710 N01 = N03 = N0.getOperand(1);
5711 N0CC = N0.getOpcode() == ISD::SMIN ? ISD::SETLT : ISD::SETGT;
5714 N00 = N0.getOperand(0);
5715 N01 = N0.getOperand(1);
5716 N02 = N0.getOperand(2);
5717 N03 = N0.getOperand(3);
5718 N0CC = cast<CondCodeSDNode>(N0.getOperand(4))->get();
5722 if (N0.getOperand(0).getOpcode() != ISD::SETCC)
5724 N00 = N0.getOperand(0).getOperand(0);
5725 N01 = N0.getOperand(0).getOperand(1);
5726 N02 = N0.getOperand(1);
5727 N03 = N0.getOperand(2);
5728 N0CC = cast<CondCodeSDNode>(N0.getOperand(0).getOperand(2))->get();
5761 static SDValue PerformMinMaxFpToSatCombine(SDValue N0, SDValue N1, SDValue N2,
5766 SDValue Fp = isSaturatingMinMax(N0, N1, N2, N3, CC, BW, Unsigned, DAG);
5783 static SDValue PerformUMinFpToSatCombine(SDValue N0, SDValue N1, SDValue N2,
5788 // be truncated versions of the setcc (N0/N1).
5789 if ((N0 != N2 &&
5790 (N2.getOpcode() != ISD::TRUNCATE || N0 != N2.getOperand(0))) ||
5791 N0.getOpcode() != ISD::FP_TO_UINT || CC != ISD::SETULT)
5804 EVT FPVT = N0.getOperand(0).getValueType();
5814 DAG.getNode(ISD::FP_TO_UINT_SAT, SDLoc(N0), NewVT, N0.getOperand(0),
5816 return DAG.getZExtOrTrunc(Sat, SDLoc(N0), N3.getValueType());
5820 SDValue N0 = N->getOperand(0);
5822 EVT VT = N0.getValueType();
5827 if (SDValue C = DAG.FoldConstantArithmetic(Opcode, DL, VT, {N0, N1}))
5831 if (N0 == N1)
5832 return N0;
5835 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
5837 return DAG.getNode(Opcode, DL, VT, N1, N0);
5845 if (SDValue RMINMAX = reassociateOps(Opcode, DL, N0, N1, N->getFlags()))
5853 bool IsSatBroken = Opcode == ISD::UMIN && N0.getOpcode() == ISD::SMAX;
5854 if ((IsSatBroken || IsOpIllegal) && (N0.isUndef() || DAG.SignBitIsZero(N0)) &&
5865 return DAG.getNode(AltOpcode, DL, VT, N0, N1);
5870 N0, N1, N0, N1, Opcode == ISD::SMIN ? ISD::SETLT : ISD::SETGT, DAG))
5873 if (SDValue S = PerformUMinFpToSatCombine(N0, N1, N0, N1, ISD::SETULT, DAG))
5892 SDLoc(N), VT, N0, N1))
5905 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
5906 EVT VT = N0.getValueType();
5908 unsigned HandOpcode = N0.getOpcode();
5913 if (N0.getNumOperands() == 0)
5920 SDValue X = N0.getOperand(0);
5926 N0.getOperand(1) == N1.getOperand(1))) {
5929 if (!N0.hasOneUse() && !N1.hasOneUse())
5948 return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
5956 if (!N0.hasOneUse() && !N1.hasOneUse())
5978 N0.getOperand(1) == N1.getOperand(1)) {
5980 if (!N0.hasOneUse() || !N1.hasOneUse())
5983 return DAG.getNode(HandOpcode, DL, VT, Logic, N0.getOperand(1));
5989 if (!N0.hasOneUse() || !N1.hasOneUse())
5999 N0.getOperand(2) == N1.getOperand(2)) {
6000 if (!N0.hasOneUse() || !N1.hasOneUse())
6002 SDValue X1 = N0.getOperand(1);
6004 SDValue S = N0.getOperand(2);
6041 auto *SVN0 = cast<ShuffleVectorSDNode>(N0);
6056 SDValue ShOp = N0.getOperand(1);
6061 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
6063 N0.getOperand(0), N1.getOperand(0));
6069 ShOp = N0.getOperand(0);
6074 if (N0.getOperand(0) == N1.getOperand(0) && ShOp.getNode()) {
6075 SDValue Logic = DAG.getNode(LogicOpcode, DL, VT, N0.getOperand(1),
6085 SDValue DAGCombiner::foldLogicOfSetCCs(bool IsAnd, SDValue N0, SDValue N1,
6088 if (!isSetCCEquivalent(N0, LL, LR, N0CC) ||
6092 assert(N0.getValueType() == N1.getValueType() &&
6101 EVT VT = N0.getValueType();
6130 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N0), OpVT, LL, RL);
6149 SDValue And = DAG.getNode(ISD::AND, SDLoc(N0), OpVT, LL, RL);
6163 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), OpVT, LL, One);
6171 N0.hasOneUse() && N1.hasOneUse()) {
6175 SDValue XorL = DAG.getNode(ISD::XOR, SDLoc(N0), OpVT, LL, LR);
6511 SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
6516 if (N0.isUndef() || N1.isUndef())
6519 if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
6525 std::swap(N0, N1);
6528 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
6529 VT.isScalarInteger() && VT.getSizeInBits() <= 64 && N0->hasOneUse()) {
6530 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6542 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
6545 SDLoc DL0(N0);
6548 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
6549 CombineTo(N0.getNode(), NewAdd);
6857 SDValue N0 = N->getOperand(0);
6861 if (!TLI.shouldFoldMaskToVariableShiftPair(N0))
6886 X = N0;
6887 else if (matchMask(N0))
7085 SDValue N0 = N->getOperand(0);
7091 if (N0 == N1)
7092 return N0;
7095 if (SDValue C = DAG.FoldConstantArithmetic(ISD::AND, DL, VT, {N0, N1}))
7099 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
7101 return DAG.getNode(ISD::AND, DL, VT, N1, N0);
7103 if (areBitwiseNotOfEachother(N0, N1))
7119 return N0;
7122 auto *MLoad = dyn_cast<MaskedLoadSDNode>(N0);
7139 bool LoadHasOtherUsers = !N0.hasOneUse();
7151 return N0;
7166 if (SDValue RAND = reassociateOps(ISD::AND, DL, N0, N1, N->getFlags()))
7171 reassociateReduction(ISD::VECREDUCE_AND, ISD::AND, DL, VT, N0, N1))
7178 if (N0.getOpcode() == ISD::OR &&
7179 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchSubset))
7182 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
7183 SDValue N0Op0 = N0.getOperand(0);
7204 if (ISD::isExtOpcode(N0.getOpcode())) {
7205 unsigned ExtOpc = N0.getOpcode();
7206 SDValue N0Op0 = N0.getOperand(0);
7209 N0->hasOneUse() && N0Op0->hasOneUse()) {
7228 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7229 N0.getValueSizeInBits() == N0.getOperand(0).getScalarValueSizeInBits() &&
7230 N0.getOperand(0).getOpcode() == ISD::LOAD &&
7231 N0.getOperand(0).getResNo() == 0) ||
7232 (N0.getOpcode() == ISD::LOAD && N0.getResNo() == 0)) {
7234 cast<LoadSDNode>((N0.getOpcode() == ISD::LOAD) ? N0 : N0.getOperand(0));
7301 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
7329 if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N))
7332 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() && N1C &&
7333 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) {
7334 SDValue Ext = N0.getOperand(0);
7347 N0.getOperand(1));
7352 if (auto *GN0 = dyn_cast<MaskedGatherSDNode>(N0)) {
7375 if (N1C && N0.getOpcode() == ISD::LOAD && !VT.isVector())
7388 if (SDValue Combined = visitANDLike(N0, N1, N))
7392 if (N0.getOpcode() == N1.getOpcode())
7396 if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG))
7398 if (SDValue R = foldLogicOfShifts(N, N1, N0, DAG))
7454 if (ISD::isUNINDEXEDLoad(N0.getNode()) &&
7455 (ISD::isEXTLoad(N0.getNode()) ||
7456 (ISD::isSEXTLoad(N0.getNode()) && N0.hasOneUse()))) {
7457 auto *LN0 = cast<LoadSDNode>(N0);
7468 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(),
7471 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
7477 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
7478 if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
7479 N0.getOperand(1), false))
7511 if (IsAndZeroExtMask(N0, N1))
7512 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
7521 if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG))
7528 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
7542 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
7543 std::swap(N0, N1);
7545 std::swap(N0, N1);
7546 if (N0.getOpcode() == ISD::AND) {
7547 if (!N0->hasOneUse())
7549 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
7555 N0 = N0.getOperand(0);
7569 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
7570 std::swap(N0, N1);
7571 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
7573 if (!N0->hasOneUse() || !N1->hasOneUse())
7576 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
7584 SDValue N00 = N0->getOperand(0);
7657 SDValue N0 = N.getOperand(0);
7658 unsigned Opc0 = N0.getOpcode();
7667 N1C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
7696 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
7704 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
7729 Parts[MaskByteOffset] = N0.getOperand(0).getNode();
7755 SelectionDAG &DAG, SDNode *N, SDValue N0,
7761 if (N0.getOpcode() != ISD::AND || N1.getOpcode() != ISD::AND)
7764 if (!N0->hasOneUse() || !N1->hasOneUse())
7766 ConstantSDNode *Mask0 = isConstOrConstSplat(N0.getOperand(1));
7773 SDValue Shift0 = N0.getOperand(0);
7798 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
7808 if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N0, N1, VT))
7812 if (SDValue BSwap = matchBSwapHWordOrAndAnd(TLI, DAG, N, N1, N0, VT))
7822 if (isBSwapHWordPair(N0, Parts)) {
7826 } else if (N0.getOpcode() == ISD::OR) {
7830 SDValue N00 = N0.getOperand(0);
7831 SDValue N01 = N0.getOperand(1);
7861 SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, const SDLoc &DL) {
7865 if (!LegalOperations && (N0.isUndef() || N1.isUndef()))
7868 if (SDValue V = foldLogicOfSetCCs(false, N0, N1, DL))
7872 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
7874 (N0->hasOneUse() || N1->hasOneUse())) {
7878 getAsNonOpaqueConstant(N0.getOperand(1))) {
7886 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
7888 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
7889 N0.getOperand(0), N1.getOperand(0));
7898 if (N0.getOpcode() == ISD::AND &&
7900 N0.getOperand(0) == N1.getOperand(0) &&
7902 (N0->hasOneUse() || N1->hasOneUse())) {
7903 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
7904 N0.getOperand(1), N1.getOperand(1));
7905 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), X);
7912 static SDValue visitORCommutative(SelectionDAG &DAG, SDValue N0, SDValue N1,
7914 EVT VT = N0.getValueType();
7924 SDValue N0Resized = peekThroughResize(N0);
7955 if (sd_match(N0, m_Xor(m_Value(X), m_Specific(N1))))
7959 if (sd_match(N0, m_Xor(m_Value(X), m_Value(Y))) &&
7964 if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG))
7974 if (N0.getOpcode() == ISD::FSHL && N1.getOpcode() == ISD::SHL &&
7975 N0.getOperand(0) == N1.getOperand(0) &&
7976 peekThroughZext(N0.getOperand(2)) == peekThroughZext(N1.getOperand(1)))
7977 return N0;
7980 if (N0.getOpcode() == ISD::FSHR && N1.getOpcode() == ISD::SRL &&
7981 N0.getOperand(1) == N1.getOperand(0) &&
7982 peekThroughZext(N0.getOperand(2)) == peekThroughZext(N1.getOperand(1)))
7983 return N0;
7988 if (sd_match(N0,
8009 SDValue N0 = N->getOperand(0);
8015 if (N0 == N1)
8016 return N0;
8019 if (SDValue C = DAG.FoldConstantArithmetic(ISD::OR, DL, VT, {N0, N1}))
8023 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
8025 return DAG.getNode(ISD::OR, DL, VT, N1, N0);
8034 return N0;
8043 auto *SV0 = dyn_cast<ShuffleVectorSDNode>(N0);
8046 bool ZeroN00 = ISD::isBuildVectorAllZeros(N0.getOperand(0).getNode());
8047 bool ZeroN01 = ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode());
8087 SDValue NewLHS = ZeroN00 ? N0.getOperand(1) : N0.getOperand(0);
8100 return N0;
8111 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
8117 if (SDValue Combined = visitORLike(N0, N1, DL))
8120 if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N))
8124 if (SDValue BSwap = MatchBSwapHWord(N, N0, N1))
8126 if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1))
8130 if (SDValue ROR = reassociateOps(ISD::OR, DL, N0, N1, N->getFlags()))
8135 reassociateReduction(ISD::VECREDUCE_OR, ISD::OR, DL, VT, N0, N1))
8143 if (N0.getOpcode() == ISD::AND && N0->hasOneUse() &&
8144 ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchIntersect, true)) {
8146 {N1, N0.getOperand(1)})) {
8147 SDValue IOR = DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1);
8153 if (SDValue Combined = visitORCommutative(DAG, N0, N1, N))
8155 if (SDValue Combined = visitORCommutative(DAG, N1, N0, N))
8159 if (N0.getOpcode() == N1.getOpcode())
8164 if (SDValue Rot = MatchRotate(N0, N1, DL))
8183 if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG))
8496 // shifts of N0 + N1. If Neg == <operand size> - Pos then the OR reduces
8497 // to both (PosOpcode N0, N1, Pos) and (NegOpcode N0, N1, Neg), with the
8501 SDValue DAGCombiner::MatchFunnelPosNeg(SDValue N0, SDValue N1, SDValue Pos,
8506 EVT VT = N0.getValueType();
8516 if (matchRotateSub(InnerPos, InnerNeg, EltBits, DAG, /*IsRotate*/ N0 == N1)) {
8517 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, N0, N1,
8538 return DAG.getNode(ISD::FSHL, DL, VT, N0, N1.getOperand(0), Pos);
8543 if (IsBinOpImm(N0, ISD::SHL, 1) &&
8547 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg);
8553 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N0.getOperand(1) &&
8557 return DAG.getNode(ISD::FSHR, DL, VT, N0.getOperand(0), N1, Neg);
9508 SDValue N0 = N->getOperand(0);
9510 if (!matchAndXor(N0, 0, N1) && !matchAndXor(N0, 1, N1) &&
9511 !matchAndXor(N1, 0, N0) && !matchAndXor(N1, 1, N0))
9559 SDValue N0 = N->getOperand(0);
9561 EVT VT = N0.getValueType();
9565 if (N0.isUndef() && N1.isUndef())
9569 if (N0.isUndef())
9570 return N0;
9575 if (SDValue C = DAG.FoldConstantArithmetic(ISD::XOR, DL, VT, {N0, N1}))
9579 if (DAG.isConstantIntBuildVectorOrConstantInt(N0) &&
9581 return DAG.getNode(ISD::XOR, DL, VT, N1, N0);
9590 return N0;
9595 return N0;
9601 if (SDValue RXOR = reassociateOps(ISD::XOR, DL, N0, N1, N->getFlags()))
9606 reassociateReduction(ISD::VECREDUCE_XOR, ISD::XOR, DL, VT, N0, N1))
9611 DAG.haveNoCommonBitsSet(N0, N1))
9612 return DAG.getNode(ISD::OR, DL, VT, N0, N1, SDNodeFlags::Disjoint);
9615 // XOR(N0,MIN_SIGNED_VALUE) == ADD(N0,MIN_SIGNED_VALUE)
9622 unsigned N0Opcode = N0.getOpcode();
9625 isSetCCEquivalent(N0, LHS, RHS, CC, /*MatchStrict*/ true)) {
9634 return DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC);
9636 return DAG.getSelectCC(SDLoc(N0), LHS, RHS, N0.getOperand(2),
9637 N0.getOperand(3), NotCC);
9640 if (N0.hasOneUse()) {
9644 DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC,
9645 N0.getOperand(0), N0Opcode == ISD::STRICT_FSETCCS);
9647 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), SetCC.getValue(1));
9648 recursivelyDeleteUnusedNodes(N0.getNode());
9658 if (isOneConstant(N1) && N0Opcode == ISD::ZERO_EXTEND && N0.hasOneUse() &&
9659 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
9660 SDValue V = N0.getOperand(0);
9661 SDLoc DL0(N0);
9670 if (isOneConstant(N1) && VT == MVT::i1 && N0.hasOneUse() &&
9672 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1);
9683 if (isAllOnesConstant(N1) && N0.hasOneUse() &&
9685 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1);
9698 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::SUB &&
9699 isNullConstant(N0.getOperand(0))) {
9700 return DAG.getNode(ISD::ADD, DL, VT, N0.getOperand(1),
9705 if (isAllOnesConstant(N1) && N0.getOpcode() == ISD::ADD &&
9706 isAllOnesOrAllOnesSplat(N0.getOperand(1))) {
9707 return DAG.getNegative(N0.getOperand(0), DL, VT);
9711 if (N0Opcode == ISD::AND && N0.hasOneUse() && N0->getOperand(1) == N1) {
9712 SDValue X = N0.getOperand(0);
9720 SDValue A = N0Opcode == ISD::ADD ? N0 : N1;
9721 SDValue S = N0Opcode == ISD::SRA ? N0 : N1;
9733 if (N0 == N1)
9755 isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0))) {
9757 N0.getOperand(1));
9765 if (SDValue R = foldLogicOfShifts(N, N0, N1, DAG))
9767 if (SDValue R = foldLogicOfShifts(N, N1, N0, DAG))
9769 if (SDValue R = foldLogicTreeOfShifts(N, N0, N1, DAG))
9780 if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N))
9954 SDValue N0 = N->getOperand(0);
9961 return N0;
9967 return N0;
9981 return DAG.getNode(N->getOpcode(), dl, VT, N0, Amt);
9988 return DAG.getNode(ISD::BSWAP, dl, VT, N0);
9998 return DAG.getNode(N->getOpcode(), dl, VT, N0, NewOp1);
10001 unsigned NextOp = N0.getOpcode();
10007 bool C2 = DAG.isConstantIntBuildVectorOrConstantInt(N0.getOperand(1));
10008 if (C1 && C2 && N1.getValueType() == N0.getOperand(1).getValueType()) {
10016 {N0.getOperand(1), BitsizeC});
10024 return DAG.getNode(N->getOpcode(), dl, VT, N0->getOperand(0),
10033 SDValue N0 = N->getOperand(0);
10035 if (SDValue V = DAG.simplifyShift(N0, N1))
10039 EVT VT = N0.getValueType();
10044 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, DL, VT, {N0, N1}))
10056 if (N0.getOpcode() == ISD::AND) {
10057 SDValue N00 = N0->getOperand(0);
10058 SDValue N01 = N0->getOperand(1);
10083 return DAG.getNode(ISD::SHL, DL, VT, N0, NewOp1);
10087 if (N0.getOpcode() == ISD::SHL) {
10095 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange))
10105 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) {
10106 SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1));
10107 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Sum);
10116 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
10117 N0.getOpcode() == ISD::ANY_EXTEND ||
10118 N0.getOpcode() == ISD::SIGN_EXTEND) &&
10119 N0.getOperand(0).getOpcode() == ISD::SHL) {
10120 SDValue N0Op0 = N0.getOperand(0);
10149 SDValue Ext = DAG.getNode(N0.getOpcode(), DL, VT, N0Op0.getOperand(0));
10159 if (N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
10160 N0.getOperand(0).getOpcode() == ISD::SRL) {
10161 SDValue N0Op0 = N0.getOperand(0);
10177 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
10181 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) {
10192 if (N0->getFlags().hasExact()) {
10193 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount,
10196 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10198 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff);
10200 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount,
10203 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10205 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Diff);
10213 if (N0.getOpcode() == ISD::SRL &&
10214 (N0.getOperand(1) == N1 || N0.hasOneUse()) &&
10216 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount,
10219 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10224 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff);
10227 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount,
10230 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10234 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff);
10241 if (N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1) &&
10245 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0), HiBitsMask);
10252 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::OR) &&
10254 SDValue N01 = N0.getOperand(1);
10257 SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
10261 if (N0.getOpcode() == ISD::OR && N0->getFlags().hasDisjoint())
10263 return DAG.getNode(N0.getOpcode(), DL, VT, Shl0, Shl1, Flags);
10270 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
10271 N0.getOperand(0).getOpcode() == ISD::ADD &&
10272 N0.getOperand(0)->getFlags().hasNoSignedWrap() &&
10274 SDValue Add = N0.getOperand(0);
10275 SDLoc DL(N0);
10276 if (SDValue ExtC = DAG.FoldConstantArithmetic(N0.getOpcode(), DL, VT,
10280 SDValue ExtX = DAG.getNode(N0.getOpcode(), DL, VT, Add.getOperand(0));
10288 if (N0.getOpcode() == ISD::MUL && N0->hasOneUse()) {
10289 SDValue N01 = N0.getOperand(1);
10292 return DAG.getNode(ISD::MUL, DL, VT, N0.getOperand(0), Shl);
10312 return DAG.getNode(ISD::MUL, DL, VT, And, N0);
10319 if (N0.getOpcode() == ISD::VSCALE && N1C) {
10320 const APInt &C0 = N0.getConstantOperandAPInt(0);
10327 if (N0.getOpcode() == ISD::STEP_VECTOR &&
10329 const APInt &C0 = N0.getConstantOperandAPInt(0);
10460 SDValue N0 = N->getOperand(0);
10463 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && N0.hasOneUse()) {
10464 SDValue OldLHS = N0.getOperand(0);
10465 SDValue OldRHS = N0.getOperand(1);
10470 return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0),
10476 return DAG.getNode(N0.getOpcode(), DL, VT, OldLHS.getOperand(0),
10482 return DAG.getNode(N0.getOpcode(), DL, VT, NewBitReorder,
10490 SDValue N0 = N->getOperand(0);
10492 if (SDValue V = DAG.simplifyShift(N0, N1))
10496 EVT VT = N0.getValueType();
10500 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRA, DL, VT, {N0, N1}))
10506 if (DAG.ComputeNumSignBits(N0) == OpSizeInBits)
10507 return N0;
10521 if (N0.getOpcode() == ISD::SRA) {
10536 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), SumOfShifts)) {
10547 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0), ShiftValue);
10556 if (N0.getOpcode() == ISD::SHL && N1C) {
10558 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
10580 N0.getOperand(0), Amt);
10594 if ((N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB) && N1C &&
10595 N0.hasOneUse()) {
10596 bool IsAdd = N0.getOpcode() == ISD::ADD;
10597 SDValue Shl = N0.getOperand(IsAdd ? 0 : 1);
10602 isConstOrConstSplat(N0.getOperand(IsAdd ? 1 : 0))) {
10637 return DAG.getNode(ISD::SRA, DL, VT, N0, NewOp1);
10644 if (N0.getOpcode() == ISD::TRUNCATE &&
10645 (N0.getOperand(0).getOpcode() == ISD::SRL ||
10646 N0.getOperand(0).getOpcode() == ISD::SRA) &&
10647 N0.getOperand(0).hasOneUse() &&
10648 N0.getOperand(0).getOperand(1).hasOneUse() && N1C) {
10649 SDValue N0Op0 = N0.getOperand(0);
10670 if (DAG.SignBitIsZero(N0))
10671 return DAG.getNode(ISD::SRL, DL, VT, N0, N1);
10693 SDValue N0 = N->getOperand(0);
10695 if (SDValue V = DAG.simplifyShift(N0, N1))
10699 EVT VT = N0.getValueType();
10704 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SRL, DL, VT, {N0, N1}))
10722 if (N0.getOpcode() == ISD::SRL) {
10730 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchOutOfRange))
10740 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchInRange)) {
10741 SDValue Sum = DAG.getNode(ISD::ADD, DL, ShiftVT, N1, N0.getOperand(1));
10742 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Sum);
10746 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
10747 N0.getOperand(0).getOpcode() == ISD::SRL) {
10748 SDValue InnerShift = N0.getOperand(0);
10768 if (N0.hasOneUse() && InnerShift.hasOneUse() &&
10784 if (N0.getOpcode() == ISD::SHL &&
10785 (N0.getOperand(1) == N1 || N0->hasOneUse()) &&
10794 if (ISD::matchBinaryPredicate(N1, N0.getOperand(1), MatchShiftAmount,
10797 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10802 SDValue Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0), Diff);
10805 if (ISD::matchBinaryPredicate(N0.getOperand(1), N1, MatchShiftAmount,
10808 SDValue N01 = DAG.getZExtOrTrunc(N0.getOperand(1), DL, ShiftVT);
10812 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), Diff);
10819 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
10821 EVT SmallVT = N0.getOperand(0).getValueType();
10828 SDLoc DL0(N0);
10830 DAG.getNode(ISD::SRL, DL0, SmallVT, N0.getOperand(0),
10843 if (N0.getOpcode() == ISD::SRA)
10844 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1);
10849 if (N1C && N0.getOpcode() == ISD::CTLZ &&
10852 KnownBits Known = DAG.computeKnownBits(N0.getOperand(0));
10856 if (Known.One.getBoolValue()) return DAG.getConstant(0, SDLoc(N0), VT);
10861 if (UnknownBits == 0) return DAG.getConstant(1, SDLoc(N0), VT);
10870 SDValue Op = N0.getOperand(0);
10873 SDLoc DL(N0);
10886 return DAG.getNode(ISD::SRL, DL, VT, N0, NewOp1);
10951 SDValue N0 = N->getOperand(0);
10958 // fold (fshl N0, N1, 0) -> N0
10959 // fold (fshr N0, N1, 0) -> N1
10963 return IsFSHL ? N0 : N1;
10973 // fold (fsh* N0, N1, c) -> (fsh* N0, N1, c % BitWidth)
10976 return DAG.getNode(N->getOpcode(), DL, VT, N0, N1,
10982 return IsFSHL ? N0 : N1;
10986 // fold fshl(N0, undef_or_zero, C) -> shl(N0, C)
10987 // fold fshr(N0, undef_or_zero, C) -> shl(N0, BW-C)
10988 if (IsUndefOrZero(N0))
10994 ISD::SHL, DL, VT, N0,
11004 auto *LHS = dyn_cast<LoadSDNode>(N0);
11038 // fold fshl(N0, undef_or_zero, N2) -> shl(N0, N2)
11043 if (IsUndefOrZero(N0) && !IsFSHL && DAG.MaskedValueIsZero(N2, ~ModuloBits))
11046 return DAG.getNode(ISD::SHL, DL, VT, N0, N2);
11049 // fold (fshl N0, N0, N2) -> (rotl N0, N2)
11050 // fold (fshr N0, N0, N2) -> (rotr N0, N2)
11055 if (N0 == N1 && hasOperation(RotOpc, VT))
11056 return DAG.getNode(RotOpc, DL, VT, N0, N2);
11058 // Simplify, based on bits shifted out of N0/N1.
11066 SDValue N0 = N->getOperand(0);
11068 if (SDValue V = DAG.simplifyShift(N0, N1))
11072 EVT VT = N0.getValueType();
11075 if (SDValue C = DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1}))
11083 N1C->getAPIntValue().ult(DAG.ComputeNumSignBits(N0)))
11084 return DAG.getNode(ISD::SHL, DL, VT, N0, N1);
11089 DAG.computeKnownBits(N0).countMinLeadingZeros()))
11090 return DAG.getNode(ISD::SHL, DL, VT, N0, N1);
11170 SDValue N0 = N->getOperand(0);
11175 if (SDValue C = DAG.FoldConstantArithmetic(ISD::ABS, DL, VT, {N0}))
11178 if (N0.getOpcode() == ISD::ABS)
11179 return N0;
11181 if (DAG.SignBitIsZero(N0))
11182 return N0;
11189 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
11190 EVT ExtVT = cast<VTSDNode>(N0.getOperand(1))->getVT();
11197 DAG.getNode(ISD::TRUNCATE, DL, ExtVT, N0.getOperand(0))));
11205 SDValue N0 = N->getOperand(0);
11210 if (SDValue C = DAG.FoldConstantArithmetic(ISD::BSWAP, DL, VT, {N0}))
11213 if (N0.getOpcode() == ISD::BSWAP)
11214 return N0.getOperand(0);
11220 if (N0.getOpcode() == ISD::BITREVERSE && N0.hasOneUse()) {
11221 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT, N0.getOperand(0));
11228 if (BW >= 32 && N0.getOpcode() == ISD::SHL && N0.hasOneUse()) {
11229 auto *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
11236 SDValue Res = N0.getOperand(0);
11250 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
11251 N0.hasOneUse()) {
11252 auto *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
11255 SDValue NewSwap = DAG.getNode(ISD::BSWAP, DL, VT, N0.getOperand(0));
11256 unsigned InverseShift = N0.getOpcode() == ISD::SHL ? ISD::SRL : ISD::SHL;
11257 return DAG.getNode(InverseShift, DL, VT, NewSwap, N0.getOperand(1));
11268 SDValue N0 = N->getOperand(0);
11273 if (SDValue C = DAG.FoldConstantArithmetic(ISD::BITREVERSE, DL, VT, {N0}))
11277 if (N0.getOpcode() == ISD::BITREVERSE)
11278 return N0.getOperand(0);
11296 SDValue N0 = N->getOperand(0);
11301 if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTLZ, DL, VT, {N0}))
11306 if (DAG.isKnownNeverZero(N0))
11307 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, DL, VT, N0);
11313 SDValue N0 = N->getOperand(0);
11319 DAG.FoldConstantArithmetic(ISD::CTLZ_ZERO_UNDEF, DL, VT, {N0}))
11325 SDValue N0 = N->getOperand(0);
11330 if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTTZ, DL, VT, {N0}))
11335 if (DAG.isKnownNeverZero(N0))
11336 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, DL, VT, N0);
11342 SDValue N0 = N->getOperand(0);
11348 DAG.FoldConstantArithmetic(ISD::CTTZ_ZERO_UNDEF, DL, VT, {N0}))
11354 SDValue N0 = N->getOperand(0);
11360 if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTPOP, DL, VT, {N0}))
11365 if (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SHL) {
11366 if (ConstantSDNode *AmtC = isConstOrConstSplat(N0.getOperand(1))) {
11369 KnownBits KnownSrc = DAG.computeKnownBits(N0.getOperand(0));
11370 if ((N0.getOpcode() == ISD::SRL &&
11372 (N0.getOpcode() == ISD::SHL &&
11374 return DAG.getNode(ISD::CTPOP, DL, VT, N0.getOperand(0));
11386 TLI.isTruncateFree(N0, HalfVT) && TLI.isZExtFree(HalfVT, VT)) {
11388 if (DAG.MaskedValueIsZero(N0, UpperBits)) {
11390 DAG.getZExtOrTrunc(N0, DL, HalfVT));
11764 SDValue N0 = N->getOperand(0);
11772 if (!sd_match(N0, m_OneUse(m_SetCC(m_Value(Cond0), m_Value(Cond1),
11869 SDValue N0 = N->getOperand(0);
11873 EVT VT0 = N0.getValueType();
11877 if (SDValue V = DAG.simplifySelect(N0, N1, N2))
11884 if (SDValue F = extractBooleanFlip(N0, DAG, TLI, false)) {
11910 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
11911 SDValue Cond0 = N0->getOperand(0);
11912 SDValue Cond1 = N0->getOperand(1);
11923 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
11924 SDValue Cond0 = N0->getOperand(0);
11925 SDValue Cond1 = N0->getOperand(1);
11941 if (N1_2 == N2 && N0.getValueType() == N1_0.getValueType()) {
11944 SDValue And = DAG.getNode(ISD::AND, DL, N0.getValueType(), N0, N1_0);
11949 if (SDValue Combined = visitANDLike(N0, N1_0, N)) {
11960 if (N2_1 == N1 && N0.getValueType() == N2_0.getValueType()) {
11963 SDValue Or = DAG.getNode(ISD::OR, DL, N0.getValueType(), N0, N2_0);
11968 if (SDValue Combined = visitORLike(N0, N2_0, DL))
11975 if (N0.getOpcode() == ISD::USUBO && N0.getResNo() == 1 &&
11976 N2.getNode() == N0.getNode() && N2.getResNo() == 0 &&
11980 return DAG.getNode(ISD::ABDU, DL, VT, N0.getOperand(0), N0.getOperand(1));
11983 if (N0.getOpcode() == ISD::USUBO && N0.getResNo() == 1 &&
11984 N1.getNode() == N0.getNode() && N1.getResNo() == 0 &&
11989 DAG.getNode(ISD::ABDU, DL, VT, N0.getOperand(0), N0.getOperand(1)),
11994 if (N0.getOpcode() == ISD::SETCC) {
11995 SDValue Cond0 = N0.getOperand(0), Cond1 = N0.getOperand(1);
11996 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
12002 if (N0.hasOneUse() && isLegalToCombineMinNumMaxNum(DAG, N1, N2, Flags, TLI))
12013 CC == ISD::SETUGT && N0.hasOneUse() && isAllOnesConstant(N1) &&
12041 Flags = N0->getFlags();
12043 N2, N0.getOperand(2));
12051 if (SDValue NewSel = SimplifySelect(DL, N0, N1, N2))
12059 if (SDValue R = combineSelectAsExtAnd(N0, N1, N2, DL, DAG))
12597 SDValue N0 = N->getOperand(0);
12602 if (SDValue V = DAG.simplifySelect(N0, N1, N2))
12612 SDValue N0 = N->getOperand(0);
12618 if (SDValue V = DAG.simplifySelect(N0, N1, N2))
12625 if (SDValue F = extractBooleanFlip(N0, DAG, TLI, false))
12631 N0.getScalarValueSizeInBits() == N1.getScalarValueSizeInBits() &&
12632 TLI.getBooleanContents(N0.getValueType()) ==
12636 DAG.getNode(ISD::AND, DL, N0.getValueType(), N1.getOperand(1), N0));
12644 if (N0.getOpcode() == ISD::SETCC) {
12645 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
12646 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
12677 if (N0.hasOneUse() &&
12853 if (ISD::isConstantSplatVectorAllOnes(N0.getNode()))
12856 if (ISD::isConstantSplatVectorAllZeros(N0.getNode()))
12864 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
12883 SDValue N0 = N->getOperand(0);
12896 if (CC == ISD::SETEQ && !LegalTypes && N0.getValueType() == MVT::i1 &&
12898 return DAG.getSelect(DL, N2.getValueType(), N0, N3, N2);
12901 if (SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()), N0, N1,
12930 return SimplifySelectCC(DL, N0, N1, N2, N3, CC);
12942 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
12945 if (SDValue Combined = SimplifySetCC(VT, N0, N1, Cond, DL, !PreferSetCC)) {
12987 if (IsAndWithShift(N0, N1)) {
12988 AndOrOp = N0;
12990 } else if (IsAndWithShift(N1, N0)) {
12992 ShiftOrRotate = N0;
12993 } else if (IsRotateWithOp(N0, N1)) {
12995 AndOrOp = N0;
12997 } else if (IsRotateWithOp(N1, N0)) {
13000 ShiftOrRotate = N0;
13005 EVT OpVT = N0.getValueType();
13119 SDValue N0 = N->getOperand(0);
13125 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) ||
13126 !N0.hasOneUse())
13129 SDValue Op1 = N0->getOperand(1);
13130 SDValue Op2 = N0->getOperand(2);
13146 (N0->getOpcode() == ISD::VSELECT && Level >= AfterLegalizeTypes &&
13152 return DAG.getSelect(DL, VT, N0->getOperand(0), Ext1, Ext2);
13165 SDValue N0 = N->getOperand(0);
13174 if (isa<ConstantSDNode>(N0))
13175 return DAG.getNode(Opcode, DL, VT, N0);
13180 if (N0->getOpcode() == ISD::SELECT) {
13181 SDValue Op1 = N0->getOperand(1);
13182 SDValue Op2 = N0->getOperand(2);
13184 (Opcode != ISD::ZERO_EXTEND || !TLI.isZExtFree(N0.getValueType(), VT))) {
13197 return DAG.getSelect(DL, VT, N0->getOperand(0),
13208 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
13213 unsigned EVTBits = N0->getValueType(0).getScalarSizeInBits();
13218 SDValue Op = N0.getOperand(i);
13244 static bool ExtendUsesToFormExtLoad(EVT VT, SDNode *N, SDValue N0,
13249 bool isTruncFree = TLI.isTruncateFree(VT, N0.getValueType());
13250 for (SDUse &Use : N0->uses()) {
13254 if (Use.getResNo() != N0.getResNo())
13265 if (UseOp == N0)
13323 SDValue N0 = N->getOperand(0);
13325 EVT SrcVT = N0.getValueType();
13348 if (N0->getOpcode() != ISD::LOAD)
13351 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
13354 !N0.hasOneUse() || !LN0->isSimple() ||
13360 if (!ExtendUsesToFormExtLoad(DstVT, N, N0, N->getOpcode(), SetCCs, TLI))
13414 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), NewValue);
13415 ExtendSetCCUses(SetCCs, N0, NewValue, (ISD::NodeType)N->getOpcode());
13416 CombineTo(N0.getNode(), Trunc, NewChain);
13430 SDValue N0 = N->getOperand(0);
13431 if (!ISD::isBitwiseLogicOp(N0.getOpcode()) ||
13432 N0.getOperand(1).getOpcode() != ISD::Constant ||
13433 (LegalOperations && !TLI.isOperationLegal(N0.getOpcode(), VT)))
13437 SDValue N1 = N0->getOperand(0);
13455 if (N1.getOpcode() == ISD::SHL && N0.getOpcode() != ISD::AND)
13458 if (!N0.hasOneUse() || !N1.hasOneUse())
13475 APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits());
13476 SDLoc DL0(N0);
13477 SDValue And = DAG.getNode(N0.getOpcode(), DL0, VT, Shift,
13490 // N0 is dead at this point.
13491 recursivelyDeleteUnusedNodes(N0.getNode());
13546 SDValue N0, ISD::LoadExtType ExtLoadType) {
13547 SDNode *N0Node = N0.getNode();
13551 !ISD::isUNINDEXEDLoad(N0Node) || !N0.hasOneUse())
13554 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
13577 bool LegalOperations, SDNode *N, SDValue N0,
13581 if (!ISD::isNON_EXTLoad(N0.getNode()) || !ISD::isUNINDEXEDLoad(N0.getNode()))
13588 for (SDNode *User : N0->users()) {
13604 !cast<LoadSDNode>(N0)->isSimple()) &&
13605 !TLI.isLoadExtLegal(ExtLoadType, VT, N0.getValueType()))
13610 if (!N0.hasOneUse())
13611 DoXform = ExtendUsesToFormExtLoad(VT, N, N0, ExtOpc, SetCCs, TLI);
13617 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
13619 LN0->getBasePtr(), N0.getValueType(),
13621 Combiner.ExtendSetCCUses(SetCCs, N0, ExtLoad, ExtOpc);
13630 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), ExtLoad);
13638 bool LegalOperations, SDNode *N, SDValue N0,
13640 if (!N0.hasOneUse())
13643 MaskedLoadSDNode *Ld = dyn_cast<MaskedLoadSDNode>(N0);
13647 if ((LegalOperations || !cast<MaskedLoadSDNode>(N0)->isSimple()) &&
13667 SDValue N0,
13669 auto *ALoad = dyn_cast<AtomicSDNode>(N0);
13732 SDValue N0 = N->getOperand(0);
13733 if (N0.getOpcode() != ISD::SETCC)
13736 SDValue N00 = N0.getOperand(0);
13737 SDValue N01 = N0.getOperand(1);
13738 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
13744 SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags());
13755 if (SVT != N0.getValueType()) {
13775 if (N0.hasOneUse() && TLI.isOperationLegalOrCustom(ISD::SETCC, VT) &&
13801 if (Use.getResNo() != 0 || User == N0.getNode())
13823 unsigned SetCCWidth = N0.getScalarValueSizeInBits();
13839 if (!VT.isVector() && !shouldConvertSelectOfConstantsToMath(N0, VT, TLI)) {
13856 SDValue N0 = N->getOperand(0);
13865 if (N0.isUndef())
13873 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
13874 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N0.getOperand(0));
13878 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
13879 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG)
13881 N0.getOperand(0));
13884 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
13885 SDValue N00 = N0.getOperand(0);
13886 EVT ExtVT = cast<VTSDNode>(N0->getOperand(1))->getVT();
13894 if (N0.getOpcode() == ISD::TRUNCATE) {
13897 if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) {
13898 SDNode *oye = N0.getOperand(0).getNode();
13899 if (NarrowLoad.getNode() != N0.getNode()) {
13900 CombineTo(N0.getNode(), NarrowLoad);
13909 SDValue Op = N0.getOperand(0);
13911 unsigned MidBits = N0.getScalarValueSizeInBits();
13914 if (N0->getFlags().hasNoSignedWrap() ||
13932 Flags.setNoUnsignedWrap(N0->getFlags().hasNoUnsignedWrap());
13938 N0.getValueType())) {
13940 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
13942 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
13944 DAG.getValueType(N0.getValueType()));
13950 tryToFoldExtOfLoad(DAG, *this, TLI, VT, LegalOperations, N, N0,
13955 tryToFoldExtOfMaskedLoad(DAG, TLI, VT, LegalOperations, N, N0,
13966 DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::SEXTLOAD))
13971 tryToFoldExtOfAtomicLoad(DAG, TLI, VT, N0, ISD::SEXTLOAD))
13976 if (ISD::isBitwiseLogicOp(N0.getOpcode()) &&
13977 isa<LoadSDNode>(N0.getOperand(0)) &&
13978 N0.getOperand(1).getOpcode() == ISD::Constant &&
13979 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
13980 LoadSDNode *LN00 = cast<LoadSDNode>(N0.getOperand(0));
13985 bool DoXform = ExtendUsesToFormExtLoad(VT, N0.getNode(), N0.getOperand(0),
13992 APInt Mask = N0.getConstantOperandAPInt(1).sext(VT.getSizeInBits());
13993 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
13995 ExtendSetCCUses(SetCCs, N0.getOperand(0), ExtLoad, ISD::SIGN_EXTEND);
13996 bool NoReplaceTruncAnd = !N0.hasOneUse();
13999 // If N0 has multiple uses, change other uses as well.
14002 DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), And);
14003 CombineTo(N0.getNode(), TruncAnd);
14024 if (!TLI.isSExtCheaperThanZExt(N0.getValueType(), VT) &&
14026 DAG.SignBitIsZero(N0))
14027 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0, SDNodeFlags::NonNeg);
14034 if (N0.getOpcode() == ISD::SUB && N0.hasOneUse() &&
14035 isNullOrNullSplat(N0.getOperand(0)) &&
14036 N0.getOperand(1).getOpcode() == ISD::ZERO_EXTEND &&
14038 SDValue Zext = DAG.getZExtOrTrunc(N0.getOperand(1).getOperand(0), DL, VT);
14043 if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() &&
14044 isAllOnesOrAllOnesSplat(N0.getOperand(1)) &&
14045 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
14047 SDValue Zext = DAG.getZExtOrTrunc(N0.getOperand(0).getOperand(0), DL, VT);
14053 if (N0.getValueType() == MVT::i1 && isBitwiseNot(N0) && N0.hasOneUse() &&
14057 if (SDValue NewXor = visitXOR(N0.getNode())) {
14058 // Returning N0 is a form of in-visit replacement that may have
14059 // invalidated N0.
14060 if (NewXor.getNode() == N0.getNode()) {
14070 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
14131 SDValue N0 = N->getOperand(0);
14140 if (N0.isUndef())
14148 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
14150 if (N0.getOpcode() == ISD::ZERO_EXTEND)
14151 Flags.setNonNeg(N0->getFlags().hasNonNeg());
14152 return DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0), Flags);
14157 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
14158 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG)
14159 return DAG.getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, N0.getOperand(0));
14166 if (isTruncateOf(DAG, N0, Op, Known)) {
14168 (Op.getScalarValueSizeInBits() == N0.getScalarValueSizeInBits()) ?
14171 N0.getScalarValueSizeInBits(),
14176 DAG.salvageDebugInfo(*N0.getNode());
14183 if (N0.getOpcode() == ISD::TRUNCATE) {
14186 if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) {
14187 SDNode *oye = N0.getOperand(0).getNode();
14188 if (NarrowLoad.getNode() != N0.getNode()) {
14189 CombineTo(N0.getNode(), NarrowLoad);
14196 EVT SrcVT = N0.getOperand(0).getValueType();
14197 EVT MinVT = N0.getValueType();
14200 SDValue Op = N0.getOperand(0);
14205 if (N0->getFlags().hasNoSignedWrap() ||
14234 SDValue Op = N0.getOperand(0);
14238 // Transfer the debug info; the new node is equivalent to N0.
14239 DAG.transferDbgValues(N0, ZExtOrTrunc);
14245 SDValue Op = DAG.getAnyExtOrTrunc(N0.getOperand(0), DL, VT);
14250 DAG.transferDbgValues(N0, And);
14257 if (N0.getOpcode() == ISD::AND &&
14258 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
14259 N0.getOperand(1).getOpcode() == ISD::Constant &&
14260 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0), N0.getValueType()) ||
14261 !TLI.isZExtFree(N0.getValueType(), VT))) {
14262 SDValue X = N0.getOperand(0).getOperand(0);
14264 APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits());
14271 DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::ZEXTLOAD,
14276 tryToFoldExtOfMaskedLoad(DAG, TLI, VT, LegalOperations, N, N0,
14287 tryToFoldExtOfAtomicLoad(DAG, TLI, VT, N0, ISD::ZEXTLOAD))
14294 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && !TLI.isZExtFree(N0, VT) &&
14295 isa<LoadSDNode>(N0.getOperand(0)) &&
14296 N0.getOperand(1).getOpcode() == ISD::Constant &&
14297 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
14298 LoadSDNode *LN00 = cast<LoadSDNode>(N0.getOperand(0));
14304 if (!N0.hasOneUse()) {
14305 if (N0.getOpcode() == ISD::AND) {
14306 auto *AndC = cast<ConstantSDNode>(N0.getOperand(1));
14314 DoXform = ExtendUsesToFormExtLoad(VT, N0.getNode(), N0.getOperand(0),
14321 APInt Mask = N0.getConstantOperandAPInt(1).zext(VT.getSizeInBits());
14322 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
14324 ExtendSetCCUses(SetCCs, N0.getOperand(0), ExtLoad, ISD::ZERO_EXTEND);
14325 bool NoReplaceTruncAnd = !N0.hasOneUse();
14328 // If N0 has multiple uses, change other uses as well.
14331 DAG.getNode(ISD::TRUNCATE, DL, N0.getValueType(), And);
14332 CombineTo(N0.getNode(), TruncAnd);
14353 DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::ZEXTLOAD))
14359 if (N0.getOpcode() == ISD::SETCC) {
14361 SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags());
14365 N0.getValueType().getVectorElementType() == MVT::i1) {
14366 EVT N00VT = N0.getOperand(0).getValueType();
14367 if (getSetCCResultType(N00VT) == N0.getValueType())
14377 SDValue VSetCC = DAG.getNode(ISD::SETCC, DL, VT, N0.getOperand(0),
14378 N0.getOperand(1), N0.getOperand(2));
14379 return DAG.getZeroExtendInReg(VSetCC, DL, N0.getValueType());
14387 DAG.getNode(ISD::SETCC, DL, MatchingVectorType, N0.getOperand(0),
14388 N0.getOperand(1), N0.getOperand(2));
14390 N0.getValueType());
14394 EVT N0VT = N0.getValueType();
14395 EVT N00VT = N0.getOperand(0).getValueType();
14397 DL, N0.getOperand(0), N0.getOperand(1),
14400 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true))
14405 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
14406 !TLI.isZExtFree(N0, VT)) {
14407 SDValue ShVal = N0.getOperand(0);
14408 SDValue ShAmt = N0.getOperand(1);
14410 if (ShVal.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse()) {
14411 if (N0.getOpcode() == ISD::SHL) {
14431 return DAG.getNode(N0.getOpcode(), DL, VT,
14450 if (N->getFlags().hasNonNeg() && !TLI.isZExtFree(N0.getValueType(), VT)) {
14451 SDNode *CSENode = DAG.getNodeIfExists(ISD::SIGN_EXTEND, N->getVTList(), N0);
14460 SDValue N0 = N->getOperand(0);
14465 if (N0.isUndef())
14474 if (N0.getOpcode() == ISD::ANY_EXTEND || N0.getOpcode() == ISD::ZERO_EXTEND ||
14475 N0.getOpcode() == ISD::SIGN_EXTEND) {
14477 if (N0.getOpcode() == ISD::ZERO_EXTEND)
14478 Flags.setNonNeg(N0->getFlags().hasNonNeg());
14479 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0), Flags);
14485 if (N0.getOpcode() == ISD::ANY_EXTEND_VECTOR_INREG ||
14486 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG ||
14487 N0.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG)
14488 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0));
14492 if (N0.getOpcode() == ISD::TRUNCATE) {
14493 if (SDValue NarrowLoad = reduceLoadWidth(N0.getNode())) {
14494 SDNode *oye = N0.getOperand(0).getNode();
14495 if (NarrowLoad.getNode() != N0.getNode()) {
14496 CombineTo(N0.getNode(), NarrowLoad);
14505 if (N0.getOpcode() == ISD::TRUNCATE)
14506 return DAG.getAnyExtOrTrunc(N0.getOperand(0), DL, VT);
14510 if (N0.getOpcode() == ISD::AND &&
14511 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
14512 N0.getOperand(1).getOpcode() == ISD::Constant &&
14513 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0), N0.getValueType())) {
14514 SDValue X = DAG.getAnyExtOrTrunc(N0.getOperand(0).getOperand(0), DL, VT);
14515 SDValue Y = DAG.getNode(ISD::ANY_EXTEND, DL, VT, N0.getOperand(1));
14526 tryToFoldExtOfLoad(DAG, *this, TLI, VT, LegalOperations, N, N0,
14529 } else if (ISD::isNON_EXTLoad(N0.getNode()) &&
14530 ISD::isUNINDEXEDLoad(N0.getNode()) &&
14531 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
14534 if (!N0.hasOneUse())
14536 ExtendUsesToFormExtLoad(VT, N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
14538 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
14540 LN0->getBasePtr(), N0.getValueType(),
14542 ExtendSetCCUses(SetCCs, N0, ExtLoad, ISD::ANY_EXTEND);
14544 bool NoReplaceTrunc = N0.hasOneUse();
14551 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), ExtLoad);
14561 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.getNode()) &&
14562 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
14563 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
14577 if (N0.getOpcode() == ISD::SETCC) {
14579 SelectionDAG::FlagInserter FlagsInserter(DAG, N0->getFlags());
14587 EVT N00VT = N0.getOperand(0).getValueType();
14588 if (getSetCCResultType(N00VT) == N0.getValueType())
14597 return DAG.getSetCC(DL, VT, N0.getOperand(0), N0.getOperand(1),
14598 cast<CondCodeSDNode>(N0.getOperand(2))->get());
14605 DL, MatchingVectorType, N0.getOperand(0), N0.getOperand(1),
14606 cast<CondCodeSDNode>(N0.getOperand(2))->get());
14612 DL, N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, DL, VT),
14614 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true))
14629 SDValue N0 = N->getOperand(0);
14634 if (N0.getOpcode() == Opcode &&
14635 AssertVT == cast<VTSDNode>(N0.getOperand(1))->getVT())
14636 return N0;
14638 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
14639 N0.getOperand(0).getOpcode() == Opcode) {
14646 SDValue BigA = N0.getOperand(0);
14658 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
14659 N0.getOperand(0).getOpcode() == ISD::AssertSext &&
14661 SDValue BigA = N0.getOperand(0);
14678 SDValue N0 = N->getOperand(0);
14682 if (auto *AAN = dyn_cast<AssertAlignSDNode>(N0))
14683 return DAG.getAssertAlign(DL, N0.getOperand(0),
14689 switch (N0.getOpcode()) {
14695 SDValue LHS = N0.getOperand(0);
14696 SDValue RHS = N0.getOperand(1);
14704 return DAG.getNode(N0.getOpcode(), DL, N0.getValueType(), LHS, RHS);
14720 SDValue N0 = N->getOperand(0);
14749 auto *LN = dyn_cast<LoadSDNode>(N0);
14795 if (Opc == ISD::SRL || N0.getOpcode() == ISD::SRL) {
14796 SDValue SRL = Opc == ISD::SRL ? SDValue(N, 0) : N0;
14869 N0 = SRL.getOperand(0);
14878 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
14879 ExtVT == VT && TLI.isNarrowingProfitable(N, N0.getValueType(), VT)) {
14880 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
14882 N0 = N0.getOperand(0);
14887 if (!isa<LoadSDNode>(N0))
14890 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
14931 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
14962 SDValue N0 = N->getOperand(0);
14971 if (N0.isUndef())
14976 DAG.FoldConstantArithmetic(ISD::SIGN_EXTEND_INREG, DL, VT, {N0, N1}))
14980 if (ExtVTBits >= DAG.ComputeMaxSignificantBits(N0))
14981 return N0;
14984 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
14985 ExtVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
14986 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, N0.getOperand(0), N1);
14992 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
14993 SDValue N00 = N0.getOperand(0);
15004 if (ISD::isExtVecInRegOpcode(N0.getOpcode())) {
15005 SDValue N00 = N0.getOperand(0);
15007 unsigned DstElts = N0.getValueType().getVectorMinNumElements();
15009 bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
15021 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
15022 SDValue N00 = N0.getOperand(0);
15029 if (DAG.MaskedValueIsZero(N0, APInt::getOneBitSet(VTBits, ExtVTBits - 1)))
15030 return DAG.getZeroExtendInReg(N0, DL, ExtVT);
15045 if (N0.getOpcode() == ISD::SRL) {
15046 if (auto *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
15050 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
15052 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0),
15053 N0.getOperand(1));
15061 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
15062 ExtVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
15063 ((!LegalOperations && cast<LoadSDNode>(N0)->isSimple() &&
15064 N0.hasOneUse()) ||
15066 auto *LN0 = cast<LoadSDNode>(N0);
15071 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
15077 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
15078 N0.hasOneUse() && ExtVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
15079 ((!LegalOperations && cast<LoadSDNode>(N0)->isSimple()) &&
15081 auto *LN0 = cast<LoadSDNode>(N0);
15086 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
15092 if (MaskedLoadSDNode *Ld = dyn_cast<MaskedLoadSDNode>(N0)) {
15093 if (ExtVT == Ld->getMemoryVT() && N0.hasOneUse() &&
15101 CombineTo(N0.getNode(), ExtMaskedLoad, ExtMaskedLoad.getValue(1));
15107 if (auto *GN0 = dyn_cast<MaskedGatherSDNode>(N0)) {
15118 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
15125 if (ExtVTBits <= 16 && N0.getOpcode() == ISD::OR) {
15126 if (SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
15127 N0.getOperand(1), false))
15135 if (N0.getOpcode() == ISD::EXTRACT_SUBVECTOR && N0.hasOneUse() &&
15136 ISD::isExtOpcode(N0.getOperand(0).getOpcode())) {
15137 SDValue InnerExt = N0.getOperand(0);
15147 N0.getOperand(1));
15187 SDValue N0 = N->getOperand(0);
15191 if (N0.isUndef()) {
15214 SDValue N0 = N->getOperand(0);
15217 if (sd_match(N0, m_FPToUI(m_Value(FPVal))) &&
15220 return DAG.getNode(ISD::FP_TO_UINT_SAT, SDLoc(N0), VT, FPVal,
15330 SDValue N0 = N->getOperand(0);
15332 EVT SrcVT = N0.getValueType();
15337 if (N0.isUndef())
15341 if (N0.getOpcode() == ISD::TRUNCATE)
15342 return DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0));
15345 if (SDValue SaturatedTR = foldToSaturated(N, VT, N0, SrcVT, DL, TLI, DAG))
15349 if (SDValue C = DAG.FoldConstantArithmetic(ISD::TRUNCATE, DL, VT, {N0}))
15353 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
15354 N0.getOpcode() == ISD::SIGN_EXTEND ||
15355 N0.getOpcode() == ISD::ANY_EXTEND) {
15357 if (N0.getOperand(0).getValueType().bitsLT(VT))
15358 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0));
15360 if (N0.getOperand(0).getValueType().bitsGT(VT))
15361 return DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0));
15364 return N0.getOperand(0);
15369 if (!LegalTypes && N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
15370 N0.hasOneUse()) {
15371 SDValue X = N0.getOperand(0);
15372 SDValue ExtVal = N0.getOperand(1);
15395 N0->hasOneUse()) {
15397 SDValue Src = N0;
15434 if (N0.getOpcode() == ISD::SELECT && N0.hasOneUse() &&
15438 TLI.isNarrowingProfitable(N0.getNode(), SrcVT, VT))) {
15439 SDLoc SL(N0);
15440 SDValue Cond = N0.getOperand(0);
15441 SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
15442 SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
15448 if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
15451 SDValue Amt = N0.getOperand(1);
15456 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0));
15465 if (SDValue V = foldSubToUSubSat(VT, N0.getNode(), DL))
15472 if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations &&
15473 N0.hasOneUse() &&
15479 for (const SDValue &Op : N0->op_values()) {
15487 if (N0.getOpcode() == ISD::SPLAT_VECTOR &&
15492 VT, DL, DAG.getNode(ISD::TRUNCATE, DL, SVT, N0->getOperand(0)));
15500 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
15501 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
15502 N0.getOperand(0).hasOneUse()) {
15503 SDValue BuildVect = N0.getOperand(0);
15529 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
15535 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
15536 auto *LN0 = cast<LoadSDNode>(N0);
15541 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
15549 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
15555 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
15556 SDValue X = N0.getOperand(i);
15594 if (N0.getOpcode() == ISD::BITCAST && !VT.isVector()) {
15595 SDValue VecSrc = N0.getOperand(0);
15614 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
15615 SDValue N00 = N0.getOperand(0);
15621 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N0->getOperand(0)), VT,
15622 N00.getOperand(0), N0.getOperand(1));
15633 switch (N0.getOpcode()) {
15640 if (!LegalOperations && N0.hasOneUse() &&
15641 (isConstantOrConstantVector(N0.getOperand(0), true) ||
15642 isConstantOrConstantVector(N0.getOperand(1), true))) {
15646 if (VT.isScalarInteger() || TLI.isOperationLegal(N0.getOpcode(), VT)) {
15647 SDValue NarrowL = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0));
15648 SDValue NarrowR = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(1));
15649 return DAG.getNode(N0.getOpcode(), DL, VT, NarrowL, NarrowR);
15660 if (((!LegalOperations && N0.getOpcode() == ISD::UADDO_CARRY) ||
15661 TLI.isOperationLegal(N0.getOpcode(), VT)) &&
15662 N0.hasOneUse() && !N0->hasAnyUseOfValue(1)) {
15663 SDValue X = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(0));
15664 SDValue Y = DAG.getNode(ISD::TRUNCATE, DL, VT, N0.getOperand(1));
15665 SDVTList VTs = DAG.getVTList(VT, N0->getValueType(1));
15666 return DAG.getNode(N0.getOpcode(), DL, VTs, X, Y, N0.getOperand(2));
15673 if (!LegalOperations && N0.hasOneUse() &&
15674 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
15675 N0.getOperand(0).getOperand(0).getScalarValueSizeInBits() <=
15677 hasOperation(N0.getOpcode(), VT)) {
15678 return getTruncatedUSUBSAT(VT, SrcVT, N0.getOperand(0), N0.getOperand(1),
15737 SDValue N0 = N->getOperand(0);
15738 EVT SourceVT = N0.getValueType();
15750 switch (N0.getOpcode()) {
15784 SDValue LogicOp0 = N0.getOperand(0);
15785 ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1), true);
15791 if (N0.getOpcode() == ISD::OR)
15800 SDValue N0 = N->getOperand(0);
15803 if (N0.isUndef())
15814 (!LegalOperations && VT.isInteger() && N0.getValueType().isInteger() &&
15816 N0.getOpcode() == ISD::BUILD_VECTOR && N0->hasOneUse() &&
15817 cast<BuildVectorSDNode>(N0)->isConstant())
15818 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(),
15822 if (isIntOrFPConstant(N0)) {
15827 (isa<ConstantSDNode>(N0) && VT.isFloatingPoint() && !VT.isVector() &&
15829 (isa<ConstantFPSDNode>(N0) && VT.isInteger() && !VT.isVector() &&
15831 SDValue C = DAG.getBitcast(VT, N0);
15838 if (N0.getOpcode() == ISD::BITCAST)
15839 return DAG.getBitcast(VT, N0.getOperand(0));
15843 if (ISD::isBitwiseLogicOp(N0.getOpcode()) && VT.isInteger() &&
15844 !TLI.isTypeLegal(N0.getOperand(0).getValueType())) {
15851 if (IsFreeBitcast(N0.getOperand(0)) && IsFreeBitcast(N0.getOperand(1)))
15852 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
15853 DAG.getBitcast(VT, N0.getOperand(0)),
15854 DAG.getBitcast(VT, N0.getOperand(1)));
15859 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
15861 TLI.hasBigEndianPartOrdering(N0.getValueType(), DAG.getDataLayout()) ==
15868 ((!LegalOperations && cast<LoadSDNode>(N0)->isSimple()) ||
15870 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
15872 if (TLI.isLoadBitCastBeneficial(N0.getValueType(), VT, DAG,
15877 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
15897 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
15898 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
15899 N0->hasOneUse() && VT.isInteger() && !VT.isVector() &&
15900 !N0.getValueType().isVector()) {
15901 SDValue NewConv = DAG.getBitcast(VT, N0.getOperand(0));
15905 if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {
15908 APInt::getSignMask(VT.getSizeInBits() / 2), SDLoc(N0), MVT::i64);
15910 if (N0.getOpcode() == ISD::FNEG) {
15914 assert(N0.getOpcode() == ISD::FABS);
15920 FlipBit = DAG.getNode(ISD::AND, SDLoc(N0), MVT::i64, Hi, SignBit);
15924 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit);
15929 if (N0.getOpcode() == ISD::FNEG)
15932 assert(N0.getOpcode() == ISD::FABS);
15948 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() &&
15949 isa<ConstantFPSDNode>(N0.getOperand(0)) && VT.isInteger() &&
15951 unsigned OrigXWidth = N0.getOperand(1).getValueSizeInBits();
15954 SDValue X = DAG.getBitcast(IntXVT, N0.getOperand(1));
15975 if (N0.getValueType() == MVT::ppcf128 && !LegalTypes) {
15977 SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0));
15979 SDValue X = DAG.getBitcast(VT, N0.getOperand(1));
15981 SDValue XorResult = DAG.getNode(ISD::XOR, SDLoc(N0), VT, Cst, X);
15993 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit);
16002 SDValue Cst = DAG.getBitcast(VT, N0.getOperand(0));
16012 if (N0.getOpcode() == ISD::BUILD_PAIR)
16013 if (SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT))
16018 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && VT.isScalarInteger()) {
16019 SDValue SrcScalar = N0.getOperand(0);
16029 N0->getOpcode() == ISD::VECTOR_SHUFFLE && N0.hasOneUse() &&
16030 VT.getVectorNumElements() >= N0.getValueType().getVectorNumElements() &&
16031 !(VT.getVectorNumElements() % N0.getValueType().getVectorNumElements())) {
16032 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N0);
16048 SDValue SV0 = PeekThroughBitcast(N0->getOperand(0));
16049 SDValue SV1 = PeekThroughBitcast(N0->getOperand(1));
16054 VT.getVectorNumElements() / N0.getValueType().getVectorNumElements();
16075 SDValue N0 = N->getOperand(0);
16077 if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, /*PoisonOnly*/ false))
16078 return N0;
16083 if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)
16093 if (DAG.canCreateUndefOrPoison(N0, /*PoisonOnly*/ false,
16095 N0->getNumValues() != 1 || !N0->hasOneUse())
16099 N0.getOpcode() == ISD::SELECT_CC ||
16100 N0.getOpcode() == ISD::SETCC ||
16101 N0.getOpcode() == ISD::BUILD_VECTOR ||
16102 N0.getOpcode() == ISD::BUILD_PAIR ||
16103 N0.getOpcode() == ISD::VECTOR_SHUFFLE ||
16104 N0.getOpcode() == ISD::CONCAT_VECTORS;
16112 if (N0.getOpcode() == ISD::BUILD_VECTOR) {
16113 SDLoc DL(N0);
16114 EVT VT = N0.getValueType();
16115 if (llvm::ISD::isBuildVectorAllOnes(N0.getNode()) && VT.isInteger())
16117 if (llvm::ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
16119 for (const SDValue &Op : N0->op_values())
16128 for (auto [OpNo, Op] : enumerate(N0->ops())) {
16148 // N0 can mutate during iteration, so make sure to refetch the maybe poison
16181 N0 = N->getOperand(0);
16185 SmallVector<SDValue> Ops(N0->ops());
16193 if (auto *SVN = dyn_cast<ShuffleVectorSDNode>(N0)) {
16195 R = DAG.getVectorShuffle(N0.getValueType(), SDLoc(N0), Ops[0], Ops[1],
16199 R = DAG.getNode(N0.getOpcode(), SDLoc(N0), N0->getVTList(), Ops);
16300 SDValue N0 = N->getOperand(0);
16333 if (N0 == N1)
16356 if (Aggressive && isContractableFMUL(N0) && isContractableFMUL(N1)) {
16357 if (N0->use_size() > N1->use_size())
16358 std::swap(N0, N1);
16362 if (isContractableFMUL(N0) && (Aggressive || N0->hasOneUse())) {
16363 return matcher.getNode(PreferredFusedOpcode, SL, VT, N0.getOperand(0),
16364 N0.getOperand(1), N1);
16371 N1.getOperand(1), N0);
16386 if (isFusedOp(N0) && N0.hasOneUse()) {
16387 FMA = N0;
16391 E = N0;
16414 if (matcher.match(N0, ISD::FP_EXTEND)) {
16415 SDValue N00 = N0.getOperand(0);
16436 matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(1)), N0);
16452 if (isFusedOp(N0)) {
16453 SDValue N02 = N0.getOperand(2);
16459 return FoldFAddFMAFPExtFMul(N0.getOperand(0), N0.getOperand(1),
16481 if (N0.getOpcode() == ISD::FP_EXTEND) {
16482 SDValue N00 = N0.getOperand(0);
16506 N0);
16525 N0);
16537 SDValue N0 = N->getOperand(0);
16608 if (isContractableFMUL(N0) && isContractableFMUL(N1) &&
16609 (N0->use_size() > N1->use_size())) {
16611 if (SDValue V = tryToFoldXSubYZ(N0, N1))
16614 if (SDValue V = tryToFoldXYSubZ(N0, N1))
16618 if (SDValue V = tryToFoldXYSubZ(N0, N1))
16621 if (SDValue V = tryToFoldXSubYZ(N0, N1))
16626 if (matcher.match(N0, ISD::FNEG) && isContractableFMUL(N0.getOperand(0)) &&
16627 (Aggressive || (N0->hasOneUse() && N0.getOperand(0).hasOneUse()))) {
16628 SDValue N00 = N0.getOperand(0).getOperand(0);
16629 SDValue N01 = N0.getOperand(0).getOperand(1);
16639 if (matcher.match(N0, ISD::FP_EXTEND)) {
16640 SDValue N00 = N0.getOperand(0);
16665 matcher.getNode(ISD::FP_EXTEND, SL, VT, N10.getOperand(1)), N0);
16675 if (matcher.match(N0, ISD::FP_EXTEND)) {
16676 SDValue N00 = N0.getOperand(0);
16699 if (matcher.match(N0, ISD::FNEG)) {
16700 SDValue N00 = N0.getOperand(0);
16735 if (CanFuse && isFusedOp(N0) &&
16736 isContractableAndReassociableFMUL(N0.getOperand(2)) &&
16737 N0->hasOneUse() && N0.getOperand(2)->hasOneUse()) {
16739 PreferredFusedOpcode, SL, VT, N0.getOperand(0), N0.getOperand(1),
16741 N0.getOperand(2).getOperand(0),
16742 N0.getOperand(2).getOperand(1),
16758 matcher.getNode(ISD::FNEG, SL, VT, N20), N21, N0));
16763 if (isFusedOp(N0) && N0->hasOneUse()) {
16764 SDValue N02 = N0.getOperand(2);
16771 PreferredFusedOpcode, SL, VT, N0.getOperand(0), N0.getOperand(1),
16787 if (matcher.match(N0, ISD::FP_EXTEND)) {
16788 SDValue N00 = N0.getOperand(0);
16825 matcher.getNode(ISD::FP_EXTEND, SL, VT, N1201), N0));
16854 matcher.getNode(ISD::FP_EXTEND, SL, VT, N1021), N0));
16866 SDValue N0 = N->getOperand(0);
16877 SDValue FAdd = N0.getOpcode() == ISD::FADD ? N0 : N1;
16916 if (SDValue FMA = FuseFADD(N0, N1))
16918 if (SDValue FMA = FuseFADD(N1, N0))
16949 if (SDValue FMA = FuseFSUB(N0, N1))
16951 if (SDValue FMA = FuseFSUB(N1, N0))
16970 SDValue N0 = N->getOperand(0);
16972 bool N0CFP = DAG.isConstantFPBuildVectorOrConstantFP(N0);
16980 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
16984 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FADD, DL, VT, {N0, N1}))
16989 return DAG.getNode(ISD::FADD, DL, VT, N1, N0);
16996 // N0 + -0.0 --> N0 (also allowed with +0.0 and fast-math)
17000 return N0;
17009 return DAG.getNode(ISD::FSUB, DL, VT, N0, NegN1);
17014 N0, DAG, LegalOperations, ForCodeSize))
17025 if (isFMulNegTwo(N0)) {
17026 SDValue B = N0.getOperand(0);
17034 return DAG.getNode(ISD::FSUB, DL, VT, N0, Add);
17044 if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
17048 if (N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
17059 if (N1CFP && N0.getOpcode() == ISD::FADD &&
17060 DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1))) {
17061 SDValue NewC = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1);
17062 return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0), NewC);
17069 if (N0.getOpcode() == ISD::FMUL) {
17070 bool CFP00 = DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(0));
17071 bool CFP01 = DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1));
17074 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
17075 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1),
17083 N0.getOperand(0) == N1.getOperand(0)) {
17084 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1),
17086 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), NewCFP);
17095 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
17098 return DAG.getNode(ISD::FMUL, DL, VT, N0, NewCFP);
17102 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
17103 N0.getOperand(0) == N0.getOperand(1) &&
17104 N1.getOperand(0) == N0.getOperand(0)) {
17111 if (N0.getOpcode() == ISD::FADD) {
17112 bool CFP00 = DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(0));
17114 if (!CFP00 && N0.getOperand(0) == N0.getOperand(1) &&
17115 (N0.getOperand(0) == N1)) {
17125 N1.getOperand(0) == N0) {
17126 return DAG.getNode(ISD::FMUL, DL, VT, N0,
17132 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
17133 N0.getOperand(0) == N0.getOperand(1) &&
17135 N0.getOperand(0) == N1.getOperand(0)) {
17136 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0),
17143 VT, N0, N1, Flags))
17158 SDValue N0 = N->getOperand(1);
17170 {Chain, N0, NegN1});
17176 N0, DAG, LegalOperations, ForCodeSize)) {
17184 SDValue N0 = N->getOperand(0);
17186 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, true);
17194 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
17198 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FSUB, DL, VT, {N0, N1}))
17213 return N0;
17217 if (N0 == N1) {
17246 if (N0 == N1->getOperand(0))
17249 if (N0 == N1->getOperand(1))
17256 return DAG.getNode(ISD::FADD, DL, VT, N0, NegN1);
17374 SDValue N0 = N->getOperand(0);
17383 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
17387 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FMUL, DL, VT, {N0, N1}))
17391 if (DAG.isConstantFPBuildVectorOrConstantFP(N0) &&
17393 return DAG.getNode(ISD::FMUL, DL, VT, N1, N0);
17406 N0.getOpcode() == ISD::FMUL) {
17407 SDValue N00 = N0.getOperand(0);
17408 SDValue N01 = N0.getOperand(1);
17420 if (N0.getOpcode() == ISD::FADD && N0.hasOneUse() &&
17421 N0.getOperand(0) == N0.getOperand(1)) {
17424 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), MulConsts);
17429 VT, N0, N1, Flags))
17435 return DAG.getNode(ISD::FADD, DL, VT, N0, N0);
17441 DAG.getConstantFP(-0.0, DL, VT), N0, Flags);
17445 // -N0 * -N1 --> N0 * N1
17451 TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0);
17464 (N0.getOpcode() == ISD::SELECT || N1.getOpcode() == ISD::SELECT) &&
17466 SDValue Select = N0, X = N1;
17522 SDValue N0 = N->getOperand(0);
17525 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
17536 DAG.FoldConstantArithmetic(N->getOpcode(), DL, VT, {N0, N1, N2}))
17539 // (-N0 * -N1) + N2 --> (N0 * N1) + N2
17545 TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0);
17567 return matcher.getNode(ISD::FADD, DL, VT, N0, N2);
17570 if (DAG.isConstantFPBuildVectorOrConstantFP(N0) &&
17572 return matcher.getNode(ISD::FMA, DL, VT, N1, N0, N2);
17578 if (matcher.match(N2, ISD::FMUL) && N0 == N2.getOperand(0) &&
17582 ISD::FMUL, DL, VT, N0,
17587 if (matcher.match(N0, ISD::FMUL) &&
17589 DAG.isConstantFPBuildVectorOrConstantFP(N0.getOperand(1))) {
17591 ISD::FMA, DL, VT, N0.getOperand(0),
17592 matcher.getNode(ISD::FMUL, DL, VT, N1, N0.getOperand(1)), N2);
17600 return matcher.getNode(ISD::FADD, DL, VT, N0, N2);
17604 SDValue RHSNeg = matcher.getNode(ISD::FNEG, DL, VT, N0);
17610 if (matcher.match(N0, ISD::FNEG) &&
17614 return matcher.getNode(ISD::FMA, DL, VT, N0.getOperand(0),
17622 if (N1CFP && N0 == N2) {
17623 return matcher.getNode(ISD::FMUL, DL, VT, N0,
17629 if (N1CFP && matcher.match(N2, ISD::FNEG) && N2.getOperand(0) == N0) {
17630 return matcher.getNode(ISD::FMUL, DL, VT, N0,
17646 SDValue N0 = N->getOperand(0);
17653 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FMAD, DL, VT, {N0, N1, N2}))
17676 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
17677 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0, /* AllowUndefs */ true);
17740 SDValue N0 = N->getOperand(0);
17748 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
17752 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FDIV, DL, VT, {N0, N1}))
17784 return DAG.getNode(ISD::FMUL, DL, VT, N0,
17793 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
17800 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
17808 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
17838 return DAG.getNode(ISD::FMUL, DL, VT, N0, Rsqrt);
17850 return DAG.getNode(ISD::FMUL, DL, VT, N0, Div);
17857 if (SDValue RV = BuildDivEstimate(N0, N1, Flags))
17864 if (N1.getOpcode() == ISD::FSQRT && N0 == N1.getOperand(0))
17873 TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize, CostN0);
17890 SDValue N0 = N->getOperand(0);
17897 if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags))
17901 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FREM, DL, VT, {N0, N1}))
17907 // Lower frem N0, N1 => x - trunc(N0 / N1) * N1, providing N1 is an integer
17915 !Flags.hasNoSignedZeros() && !DAG.cannotBeOrderedNegativeFP(N0);
17916 SDValue Div = DAG.getNode(ISD::FDIV, DL, VT, N0, N1);
17921 N1, N0);
17924 MLA = DAG.getNode(ISD::FSUB, DL, VT, N0, Mul);
17926 return NeedsCopySign ? DAG.getNode(ISD::FCOPYSIGN, DL, VT, MLA, N0) : MLA;
17942 SDValue N0 = N->getOperand(0);
17943 if (TLI.isFsqrtCheap(N0, DAG))
17947 // TODO: If this is N0/sqrt(N0), and we reach this node before trying to
17951 return buildSqrtEstimate(N0, Flags);
17983 SDValue N0 = N->getOperand(0);
17989 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FCOPYSIGN, DL, VT, {N0, N1}))
17998 return DAG.getNode(ISD::FABS, DL, VT, N0);
18002 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
18009 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
18010 N0.getOpcode() == ISD::FCOPYSIGN)
18011 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N0.getOperand(0), N1);
18015 return DAG.getNode(ISD::FABS, DL, VT, N0);
18019 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N0, N1.getOperand(1));
18024 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, N0, N1.getOperand(0));
18033 if (SimplifyDemandedBits(N0,
18132 SDValue N0 = N->getOperand(0);
18133 if (N->getOpcode() == ISD::SINT_TO_FP && N0.getOpcode() == ISD::FP_TO_SINT &&
18134 N0.getOperand(0).getValueType() == VT)
18135 return DAG.getNode(ISD::FTRUNC, DL, VT, N0.getOperand(0));
18137 if (N->getOpcode() == ISD::UINT_TO_FP && N0.getOpcode() == ISD::FP_TO_UINT &&
18138 N0.getOperand(0).getValueType() == VT)
18139 return DAG.getNode(ISD::FTRUNC, DL, VT, N0.getOperand(0));
18145 SDValue N0 = N->getOperand(0);
18147 EVT OpVT = N0.getValueType();
18151 if (N0.isUndef())
18157 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SINT_TO_FP, DL, VT, {N0}))
18165 if (DAG.SignBitIsZero(N0))
18166 return DAG.getNode(ISD::UINT_TO_FP, DL, VT, N0);
18171 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
18174 return DAG.getSelect(DL, VT, N0, DAG.getConstantFP(-1.0, DL, VT),
18179 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
18180 N0.getOperand(0).getOpcode() == ISD::SETCC && !VT.isVector() &&
18182 return DAG.getSelect(DL, VT, N0.getOperand(0),
18193 SDValue N0 = N->getOperand(0);
18195 EVT OpVT = N0.getValueType();
18199 if (N0.isUndef())
18205 if (SDValue C = DAG.FoldConstantArithmetic(ISD::UINT_TO_FP, DL, VT, {N0}))
18213 if (DAG.SignBitIsZero(N0))
18214 return DAG.getNode(ISD::SINT_TO_FP, DL, VT, N0);
18218 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
18220 return DAG.getSelect(DL, VT, N0, DAG.getConstantFP(1.0, DL, VT),
18231 SDValue N0 = N->getOperand(0);
18234 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP)
18237 SDValue Src = N0.getOperand(0);
18239 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP;
18254 const fltSemantics &Sem = N0.getValueType().getFltSemantics();
18272 SDValue N0 = N->getOperand(0);
18277 if (N0.isUndef())
18281 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FP_TO_SINT, DL, VT, {N0}))
18288 SDValue N0 = N->getOperand(0);
18293 if (N0.isUndef())
18297 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FP_TO_UINT, DL, VT, {N0}))
18304 SDValue N0 = N->getOperand(0);
18309 if (N0.isUndef())
18315 DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, {N0}))
18322 SDValue N0 = N->getOperand(0);
18328 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FP_ROUND, DL, VT, {N0, N1}))
18332 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
18333 return N0.getOperand(0);
18336 if (N0.getOpcode() == ISD::FP_ROUND) {
18338 const bool N0IsTrunc = N0.getConstantOperandVal(1) == 1;
18351 if (N0.getOperand(0).getValueType() == MVT::f80 && VT == MVT::f16)
18361 ISD::FP_ROUND, DL, VT, N0.getOperand(0),
18370 if (N0.getOpcode() == ISD::FCOPYSIGN && N0->hasOneUse() &&
18372 N0.getValueType())) {
18373 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
18374 N0.getOperand(0), N1);
18376 return DAG.getNode(ISD::FCOPYSIGN, DL, VT, Tmp, N0.getOperand(1));
18386 SDValue N0 = N->getOperand(0);
18399 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FP_EXTEND, DL, VT, {N0}))
18403 if (N0.getOpcode() == ISD::FP16_TO_FP &&
18405 return DAG.getNode(ISD::FP16_TO_FP, DL, VT, N0.getOperand(0));
18409 if (N0.getOpcode() == ISD::FP_ROUND && N0.getConstantOperandVal(1) == 1) {
18410 SDValue In = N0.getOperand(0);
18413 return DAG.getNode(ISD::FP_ROUND, DL, VT, In, N0.getOperand(1));
18418 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
18419 TLI.isLoadExtLegalOrCustom(ISD::EXTLOAD, VT, N0.getValueType())) {
18420 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
18423 LN0->getBasePtr(), N0.getValueType(),
18427 N0.getNode(),
18428 DAG.getNode(ISD::FP_ROUND, SDLoc(N0), N0.getValueType(), ExtLoad,
18429 DAG.getIntPtrConstant(1, SDLoc(N0), /*isTarget=*/true)),
18441 SDValue N0 = N->getOperand(0);
18445 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FCEIL, SDLoc(N), VT, {N0}))
18452 SDValue N0 = N->getOperand(0);
18456 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FTRUNC, SDLoc(N), VT, {N0}))
18462 switch (N0.getOpcode()) {
18470 return N0;
18477 SDValue N0 = N->getOperand(0);
18480 if (DAG.isConstantFPBuildVectorOrConstantFP(N0))
18481 return DAG.getNode(ISD::FFREXP, SDLoc(N), N->getVTList(), N0);
18486 SDValue N0 = N->getOperand(0);
18490 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FFLOOR, SDLoc(N), VT, {N0}))
18497 SDValue N0 = N->getOperand(0);
18502 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FNEG, SDLoc(N), VT, {N0}))
18506 TLI.getNegatedExpression(N0, DAG, LegalOperations, ForCodeSize))
18513 if (N0.getOpcode() == ISD::FSUB &&
18515 N->getFlags().hasNoSignedZeros()) && N0.hasOneUse()) {
18516 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0.getOperand(1),
18517 N0.getOperand(0));
18527 SDValue N0 = N->getOperand(0);
18537 if (SDValue C = DAG.FoldConstantArithmetic(Opc, SDLoc(N), VT, {N0, N1}))
18541 if (DAG.isConstantFPBuildVectorOrConstantFP(N0) &&
18543 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
18578 Opc, SDLoc(N), VT, N0, N1, Flags))
18585 SDValue N0 = N->getOperand(0);
18590 if (SDValue C = DAG.FoldConstantArithmetic(ISD::FABS, DL, VT, {N0}))
18594 if (N0.getOpcode() == ISD::FABS)
18599 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
18600 return DAG.getNode(ISD::FABS, DL, VT, N0.getOperand(0));
20351 SDValue N0 = Value.getOperand(0);
20352 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
20353 Chain == SDValue(N0.getNode(), 1)) {
20354 LoadSDNode *LD = cast<LoadSDNode>(N0);
20436 DAG.getLoad(NewVT, SDLoc(N0), LD->getChain(), NewPtr,
20449 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
25128 SDValue N0 = N->getOperand(0);
25132 EVT WideVT = N0.getValueType();
25137 auto *WideShuffleVector = dyn_cast<ShuffleVectorSDNode>(N0);
25482 SDValue N0 = Shuf->getOperand(0), N1 = Shuf->getOperand(1);
25483 if (N0.getOpcode() != ISD::CONCAT_VECTORS || N0.getNumOperands() != 2 ||
25485 !N0.getOperand(1).isUndef() || !N1.getOperand(1).isUndef())
25519 SDValue X = N0.getOperand(0), Y = N1.getOperand(0);
25532 SDValue N0 = N->getOperand(0);
25538 EVT ConcatVT = N0.getOperand(0).getValueType();
25550 N0 = DAG.getVectorShuffle(ConcatVT, SDLoc(N), N0.getOperand(0),
25551 N0.getOperand(1),
25554 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, N0, N1);
25582 if (OpIdx < (int)N0.getNumOperands())
25583 Ops.push_back(N0.getOperand(OpIdx));
25585 Ops.push_back(N1.getOperand(OpIdx - N0.getNumOperands()));
25612 SDValue N0 = SVN->getOperand(0);
25615 if (!N0->hasOneUse())
25624 bool N0AnyConst = isAnyConstantBuildVector(N0);
25626 if (N0AnyConst && !N1AnyConst && !ISD::isBuildVectorAllZeros(N0.getNode()))
25635 auto *BV0 = dyn_cast<BuildVectorSDNode>(N0);
25647 SDValue &S = (M < (int)NumElts ? N0 : N1);
25753 SDValue N0 = SVN->getOperand(0);
25760 return DAG.getBitcast(VT, DAG.getNode(Opcode, SDLoc(SVN), *OutVT, N0));
25901 SDValue N0 = peekThroughBitcasts(SVN->getOperand(0));
25903 unsigned Opcode = N0.getOpcode();
25907 SDValue N00 = N0.getOperand(0);
25912 unsigned ExtDstSizeInBits = N0.getScalarValueSizeInBits();
26258 SDValue N0 = N->getOperand(0);
26261 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
26264 if (N0.isUndef() && N1.isUndef())
26270 if (N0 == N1)
26271 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
26275 if (N0.isUndef())
26291 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, NewMask);
26308 if (N0.hasOneUse() && TLI.isExtractVecEltCheap(VT, SplatIndex) &&
26309 TLI.isBinOp(N0.getOpcode()) && N0->getNumValues() == 1) {
26312 SDValue L = N0.getOperand(0), R = N0.getOperand(1);
26319 DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR, N0->getFlags());
26328 N0.hasOneUse()) {
26329 if (N0.getOpcode() == ISD::SCALAR_TO_VECTOR && SplatIndex == 0)
26330 return DAG.getSplatBuildVector(VT, SDLoc(N), N0.getOperand(0));
26332 if (N0.getOpcode() == ISD::INSERT_VECTOR_ELT)
26333 if (auto *Idx = dyn_cast<ConstantSDNode>(N0.getOperand(2)))
26335 return DAG.getSplatBuildVector(VT, SDLoc(N), N0.getOperand(1));
26339 if (N0.getOpcode() == ISD::BITCAST && N0.getOperand(0).hasOneUse() &&
26341 (N0.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR ||
26342 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR)) {
26343 EVT N00VT = N0.getOperand(0).getValueType();
26348 SDValue Op = DAG.getZExtOrTrunc(N0.getOperand(0).getOperand(0),
26358 SDNode *V = N0.getNode();
26379 return N0;
26388 return N0;
26429 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
26433 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
26441 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N1.isUndef() &&
26442 N0.getNumOperands() == 2 &&
26443 N0.getOperand(0) == N0.getOperand(1)) {
26455 SDValue UndefVec = DAG.getUNDEF(N0.getOperand(0).getValueType());
26457 N0.getOperand(0), UndefVec);
26516 if (SDValue InsertN1 = ShuffleToInsert(N0, N1, Mask))
26518 if (N0.getOpcode() == ISD::CONCAT_VECTORS) {
26521 if (SDValue InsertN0 = ShuffleToInsert(N1, N0, CommuteMask))
26547 (DemandedLHS.isZero() || DAG.MaskedVectorIsZero(N0, DemandedLHS)) &&
26569 VT, DAG.getVectorShuffle(IntVT, DL, DAG.getBitcast(IntVT, N0),
26574 VT, DAG.getNode(ISD::AND, DL, IntVT, DAG.getBitcast(IntVT, N0),
26589 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
26593 SDValue BC0 = peekThroughOneUseBitcasts(N0);
26676 // This shuffle index refers to the inner shuffle N0. Lookup the inner
26769 N0.getOpcode() != ISD::VECTOR_SHUFFLE) {
26777 bool HasSameOp0 = N0 == SV0;
26779 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
26786 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE &&
26788 cast<ShuffleVectorSDNode>(N0)->isSplat() &&
26828 unsigned SrcOpcode = N0.getOpcode();
26829 if (TLI.isBinOp(SrcOpcode) && N->isOnlyUserOf(N0.getNode()) &&
26833 SDValue Op00 = N0.getOperand(0);
26834 SDValue Op01 = N0.getOperand(1);
26849 SDValue InnerN = Commute ? N1 : N0;
27011 SDValue N0 = N->getOperand(0);
27018 return N0;
27023 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
27034 VT, N0, N1.getOperand(0), N2);
27044 // insert_subvector(N0, extract_subvector(N0, N2), N2) --> N0
27045 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && N1.getOperand(0) == N0 &&
27047 return N0;
27051 if (N0.isUndef() && N1.getOpcode() == ISD::SPLAT_VECTOR)
27059 if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST &&
27071 // i.e. INSERT_SUBVECTOR (BITCAST N0) (BITCAST N1) N2 ->
27072 // BITCAST (INSERT_SUBVECTOR N0 N1 N2)
27073 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST) {
27074 SDValue CN0 = N0.getOperand(0);
27090 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR &&
27091 N0.getOperand(1).getValueType() == N1.getValueType() &&
27092 N0.getOperand(2) == N2)
27093 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0.getOperand(0),
27099 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR &&
27102 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0,
27108 if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) &&
27110 SDValue N0Src = peekThroughBitcasts(N0);
27114 if ((N0.isUndef() || N0SrcSVT == N1SrcSVT) &&
27146 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR && N0.hasOneUse() &&
27147 N1.getValueType() == N0.getOperand(1).getValueType()) {
27148 unsigned OtherIdx = N0.getConstantOperandVal(2);
27152 N0.getOperand(0), N1, N2);
27154 return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N0.getNode()),
27155 VT, NewOp, N0.getOperand(1), N0.getOperand(2));
27161 if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0.hasOneUse() &&
27162 N0.getOperand(0).getValueType() == N1.getValueType() &&
27163 N0.getOperand(0).getValueType().isScalableVector() ==
27166 SmallVector<SDValue, 8> Ops(N0->ops());
27179 SDValue N0 = N->getOperand(0);
27182 if (N0->getOpcode() == ISD::FP16_TO_FP)
27183 return N0->getOperand(0);
27192 SDValue N0 = N->getOperand(0);
27196 if (!TLI.shouldKeepZExtForFP16Conv() && N0->getOpcode() == ISD::AND) {
27197 ConstantSDNode *AndConst = getAsNonOpaqueConstant(N0.getOperand(1));
27199 return DAG.getNode(Op, SDLoc(N), N->getValueType(0), N0.getOperand(0));
27207 N->getValueType(0), {N0});
27212 SDValue N0 = N->getOperand(0);
27215 if (N0->getOpcode() == ISD::BF16_TO_FP)
27216 return N0->getOperand(0);
27227 SDValue N0 = N->getOperand(0);
27228 EVT VT = N0.getValueType();
27235 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getVectorElementType(), N0,
27249 DAG.ComputeNumSignBits(N0) == VT.getScalarSizeInBits())
27250 return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), N0);
27255 if (N0.getOpcode() == ISD::INSERT_SUBVECTOR &&
27256 TLI.isTypeLegal(N0.getOperand(1).getValueType())) {
27257 SDValue Vec = N0.getOperand(0);
27258 SDValue Subvec = N0.getOperand(1);
27260 (N0.getOperand(0).isUndef() || isNullOrNullSplat(Vec))) ||
27262 (N0.getOperand(0).isUndef() || isAllOnesOrAllOnesSplat(Vec))))
27270 (N0.getOpcode() == ISD::SIGN_EXTEND ||
27271 N0.getOpcode() == ISD::ZERO_EXTEND ||
27272 N0.getOpcode() == ISD::ANY_EXTEND) &&
27273 TLI.isOperationLegalOrCustom(Opcode, N0.getOperand(0).getValueType())) {
27275 N0.getOperand(0).getValueType().getScalarType(),
27276 N0.getOperand(0));
27277 return DAG.getNode(N0.getOpcode(), SDLoc(N), N->getValueType(0), Red);
27544 SDValue N0 = N->getOperand(0);
27555 SDValue Src0 = DAG.getSplatSourceVector(N0, Index0);
27559 bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR &&
27577 if (N0.getOpcode() == ISD::BUILD_VECTOR && N0.getOpcode() == N1.getOpcode()) {
27609 SDValue N0 = N->getOperand(0);
27614 SDValue Src0 = DAG.getSplatSourceVector(N0, Index0);
27616 (N0.getOpcode() == ISD::SPLAT_VECTOR ||
27620 EVT SrcVT = N0.getValueType();
27750 SDValue DAGCombiner::SimplifySelect(const SDLoc &DL, SDValue N0, SDValue N1,
27752 assert(N0.getOpcode() == ISD::SETCC &&
27755 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
27756 cast<CondCodeSDNode>(N0.getOperand(2))->get());
27765 const SDNodeFlags Flags = N0->getFlags();
27766 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
27767 N0.getValueType(),
27974 /// Try to fold an expression of the form (N0 cond N1) ? N2 : N3 to a shift and
27976 SDValue DAGCombiner::foldSelectCCToShiftAnd(const SDLoc &DL, SDValue N0,
27983 EVT XType = N0.getValueType();
27994 if (!(isAllOnesConstant(N1) || (isNullConstant(N1) && N0 == N2)))
27999 if (!(isNullConstant(N1) || (isOneConstant(N1) && N0 == N2)))
28012 SDValue Shift = DAG.getNode(ISD::SRL, DL, XType, N0, ShiftAmt);
28032 SDValue Shift = DAG.getNode(ISD::SRA, DL, XType, N0, ShiftAmt);
28048 SDValue N0 = N->getOperand(0);
28060 // TODO: Do we really need to check N0 (the condition operand of the select)?
28062 if (!N0->hasOneUse() || !N1->hasOneUse() || !N2->hasOneUse())
28074 SDValue NewSel = DAG.getSelect(DL, N10.getValueType(), N0, N10, N20);
28088 SDValue NewSel = DAG.getSelect(DL, N11.getValueType(), N0, N11, N21);
28103 SDValue N0 = N->getOperand(0);
28108 if (IsFree || N0.getOpcode() != ISD::BITCAST || !N0.hasOneUse())
28111 SDValue Int = N0.getOperand(0);
28121 if (N0.getValueType().isVector()) {
28124 SignMask = APInt::getSignMask(N0.getScalarValueSizeInBits());
28134 SDLoc DL(N0);
28146 const SDLoc &DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3,
28148 if (!TLI.reduceSelectOfFPConstantLoads(N0.getValueType()))
28187 DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()), N0, N1, CC);
28198 /// Simplify an expression of the form (N0 cond N1) ? N2 : N3
28200 SDValue DAGCombiner::SimplifySelectCC(const SDLoc &DL, SDValue N0, SDValue N1,
28206 EVT CmpOpVT = N0.getValueType();
28214 if (SDValue SCC = DAG.FoldSetCC(CmpResVT, N0, N1, CC, DL)) {
28224 convertSelectOfFPConstantsToLoadOffset(DL, N0, N1, N2, N3, CC))
28227 if (SDValue V = foldSelectCCToShiftAnd(DL, N0, N1, N2, N3, CC))
28236 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
28237 N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) {
28238 SDValue AndLHS = N0->getOperand(0);
28239 auto *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
28247 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
28252 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
28281 SCC = DAG.getSetCC(DL, CmpResVT, N0, N1, CC);
28284 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
28321 // If the other operand is cttz/cttz_zero_undef of N0, and cttz is
28325 N0 == Count.getOperand(0) &&
28327 return DAG.getNode(ISD::CTTZ, DL, VT, N0);
28328 // If the other operand is ctlz/ctlz_zero_undef of N0, and ctlz is
28332 N0 == Count.getOperand(0) &&
28334 return DAG.getNode(ISD::CTLZ, DL, VT, N0);
28347 ISD::SRA, DL, CmpOpVT, N0,
28353 if (SDValue S = PerformMinMaxFpToSatCombine(N0, N1, N2, N3, CC, DAG))
28355 if (SDValue S = PerformUMinFpToSatCombine(N0, N1, N2, N3, CC, DAG))
28357 if (SDValue ABD = foldSelectToABD(N0, N1, N2, N3, CC, DL))
28364 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
28369 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);