Lines Matching defs:SU
105 for (const SUnit *SU : L) {
106 dbgs() << "SU(" << SU->NodeNum << ")";
107 if (SU != L.back())
237 /// MO is an operand of SU's instruction that defines a physical register. Adds
238 /// data dependencies from SU to any uses of the physical register.
239 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
240 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
249 const MCInstrDesc &DefMIDesc = SU->getInstr()->getDesc();
255 SUnit *UseSU = I->SU;
256 if (UseSU == SU)
266 Dep = SDep(SU, SDep::Artificial);
270 SU->hasPhysRegDefs = true;
278 Dep = SDep(SU, SDep::Data, UseReg);
281 Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
286 ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOpIdx, Dep, &SchedModel);
295 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
296 MachineInstr *MI = SU->getInstr();
315 SUnit *DefSU = I->SU;
320 if (DefSU != SU &&
322 SDep Dep(SU, Kind, DefMO.getReg());
327 ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep,
335 SU->hasPhysRegUses = true;
340 Uses.insert(PhysRegSUOper(SU, OperIdx, Unit));
344 addPhysRegDataDeps(SU, OperIdx);
353 if (MO.isDead() && SU->isCall) {
365 if (!I->SU->isCall)
374 Defs.insert(PhysRegSUOper(SU, OperIdx, Unit));
405 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
406 MachineInstr *MI = SU->getInstr();
453 SUnit *UseSU = I->SU;
455 SDep Dep(SU, SDep::Data, Reg);
458 ST.adjustSchedDependency(SU, OperIdx, UseSU, I->OperandIndex, Dep,
491 SUnit *DefSU = V2SU.SU;
497 if (DefSU == SU)
499 SDep Dep(SU, SDep::Output, Reg);
509 V2SU.SU = SU;
516 CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
525 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
526 const MachineInstr *MI = SU->getInstr();
535 CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
544 if (V2SU.SU == SU)
547 V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg));
582 SUnit *SU = newSUnit(&MI);
583 MISUnitMap[&MI] = SU;
585 SU->isCall = MI.isCall();
586 SU->isCommutable = MI.isCommutable();
588 // Assign the Latency field of SU using target-provided information.
589 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
600 const MCSchedClassDesc *SC = getSchedClass(SU);
606 SU->hasReservedResource = true;
609 SU->isUnbuffered = true;
635 /// Adds SU to the SUList of V. If Map grows huge, reduce its size by calling
637 void inline insert(SUnit *SU, ValueType V) {
638 MapVector::operator[](V).push_back(SU);
675 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
678 addChainDependencies(SU, I.second,
682 void ScheduleDAGInstrs::addChainDependencies(SUnit *SU,
687 addChainDependencies(SU, Itr->second,
696 for (auto *SU : SUs)
697 SU->addPredBarrier(BarrierChain);
762 // objects. The SU is then inserted in the SUList(s) mapped from the
769 // Certain memory accesses are known to not alias any SU in Stores
824 SUnit *SU = MISUnitMap[&MI];
825 assert(SU && "No SUnit mapped to this MI");
835 PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI);
859 addPhysRegDeps(SU, j);
862 addVRegDefDeps(SU, j);
876 addPhysRegDeps(SU, j);
878 addVRegUseDeps(SU, j);
888 if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) {
889 SDep Dep(SU, SDep::Artificial);
890 Dep.setLatency(SU->Latency - 1);
904 BarrierChain->addPredBarrier(SU);
905 BarrierChain = SU;
907 LLVM_DEBUG(dbgs() << "Global memory object and new barrier chain: SU("
924 BarrierChain->addPredBarrier(SU);
926 FPExceptions.insert(SU, UnknownValue);
942 BarrierChain->addPredBarrier(SU);
946 // SU depends on.
954 addChainDependencies(SU, Stores);
955 addChainDependencies(SU, NonAliasStores);
956 addChainDependencies(SU, Loads);
957 addChainDependencies(SU, NonAliasLoads);
960 Stores.insert(SU, UnknownValue);
969 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
970 addChainDependencies(SU, (ThisMayAlias ? Loads : NonAliasLoads), V);
979 (ThisMayAlias ? Stores : NonAliasStores).insert(SU, V);
983 addChainDependencies(SU, Loads, UnknownValue);
984 addChainDependencies(SU, Stores, UnknownValue);
986 } else { // SU is a load.
989 addChainDependencies(SU, Stores);
990 addChainDependencies(SU, NonAliasStores);
992 Loads.insert(SU, UnknownValue);
1000 addChainDependencies(SU, (ThisMayAlias ? Stores : NonAliasStores), V);
1003 (ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V);
1006 addChainDependencies(SU, Stores, UnknownValue);
1060 // Insert all SU's NodeNums into a vector and sort it.
1065 for (const auto *SU : SUs)
1066 NodeNums.push_back(SU->NodeNum);
1070 for (const auto *SU : SUs)
1071 NodeNums.push_back(SU->NodeNum);
1075 // The N last elements in NodeNums will be removed, and the SU with
1088 LLVM_DEBUG(dbgs() << "Inserting new barrier chain: SU("
1092 LLVM_DEBUG(dbgs() << "Keeping old barrier chain: SU("
1175 void ScheduleDAGInstrs::dumpNode(const SUnit &SU) const {
1177 dumpNodeName(SU);
1179 dbgs() << " [TopReadyCycle = " << SU.TopReadyCycle
1180 << ", BottomReadyCycle = " << SU.BotReadyCycle << "]";
1182 SU.getInstr()->dump();
1190 for (const SUnit &SU : SUnits)
1191 dumpNodeAll(SU);
1197 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1200 if (SU == &EntrySU)
1202 else if (SU == &ExitSU)
1205 SU->getInstr()->print(oss, /*IsStandalone=*/true);
1270 bool isVisited(const SUnit *SU) const {
1271 return R.DFSNodeData[SU->NodeNum].SubtreeID
1277 void visitPreorder(const SUnit *SU) {
1278 R.DFSNodeData[SU->NodeNum].InstrCount =
1279 SU->getInstr()->isTransient() ? 0 : 1;
1285 void visitPostorderNode(const SUnit *SU) {
1288 R.DFSNodeData[SU->NodeNum].SubtreeID = SU->NodeNum;
1289 RootData RData(SU->NodeNum);
1290 RData.SubInstrCount = SU->getInstr()->isTransient() ? 0 : 1;
1297 unsigned InstrCount = R.DFSNodeData[SU->NodeNum].InstrCount;
1298 for (const SDep &PredDep : SU->Preds) {
1303 joinPredSubtree(PredDep, SU, /*CheckLimit=*/false);
1310 RootSet[PredNum].ParentNodeID = SU->NodeNum;
1321 RootSet[SU->NodeNum] = RData;
1360 LLVM_DEBUG(dbgs() << " SU(" << Idx << ") in tree "
1434 void follow(const SUnit *SU) {
1435 DFSStack.emplace_back(SU, SU->Preds.begin());
1455 static bool hasDataSucc(const SUnit *SU) {
1456 for (const SDep &SuccDep : SU->Succs) {
1471 for (const SUnit &SU : SUnits) {
1472 if (Impl.isVisited(&SU) || hasDataSucc(&SU))
1476 Impl.visitPreorder(&SU);
1477 DFS.follow(&SU);