Lines Matching defs:OperIdx

239 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
240   const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
250   bool ImplicitPseudoDef = (OperIdx >= DefMIDesc.getNumOperands() &&
281         Dep.setLatency(SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
286       ST.adjustSchedDependency(SU, OperIdx, UseSU, UseOpIdx, Dep, &SchedModel);
294 /// physical register referenced at OperIdx.
295 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
297   MachineOperand &MO = MI->getOperand(OperIdx);
325               SchedModel.computeOutputLatency(MI, OperIdx, DefInstr));
327         ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep,
340       Uses.insert(PhysRegSUOper(SU, OperIdx, Unit));
344     addPhysRegDataDeps(SU, OperIdx);
374       Defs.insert(PhysRegSUOper(SU, OperIdx, Unit));
401 /// the virtual register defined at OperIdx.
405 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
407   MachineOperand &MO = MI->getOperand(OperIdx);
425            llvm::drop_begin(MI->operands(), OperIdx + 1))
456         Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
458         ST.adjustSchedDependency(SU, OperIdx, UseSU, I->OperandIndex, Dep,
501       SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
520 /// virtual register used at OperIdx is mapped to an SUnit. Add a register
525 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
529   const MachineOperand &MO = MI->getOperand(OperIdx);
535   CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));