Lines Matching defs:VirtReg
202 Register VirtReg; ///< Virtual register number.
208 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {}
211 return Register::virtReg2Index(VirtReg);
351 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) {
352 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
355 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const {
356 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg));
363 void assignDanglingDebugValues(MachineInstr &Def, Register VirtReg,
366 Register VirtReg);
367 bool defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
369 bool useVirtReg(MachineInstr &MI, MachineOperand &MO, Register VirtReg);
381 Register traceCopies(Register VirtReg) const;
385 int getStackSpaceFor(Register VirtReg);
386 void spill(MachineBasicBlock::iterator Before, Register VirtReg,
388 void reload(MachineBasicBlock::iterator Before, Register VirtReg,
391 bool mayLiveOut(Register VirtReg);
392 bool mayLiveIn(Register VirtReg);
467 int RegAllocFastImpl::getStackSpaceFor(Register VirtReg) {
469 int SS = StackSlotForVirtReg[VirtReg];
475 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
481 StackSlotForVirtReg[VirtReg] = FrameIdx;
494 /// Returns false if \p VirtReg is known to not live out of the current block.
495 bool RegAllocFastImpl::mayLiveOut(Register VirtReg) {
496 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) {
507 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) {
509 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
517 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
526 for (const MachineInstr &UseInst : MRI->use_nodbg_instructions(VirtReg)) {
528 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
538 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
547 /// Returns false if \p VirtReg is known to not be live into the current block.
548 bool RegAllocFastImpl::mayLiveIn(Register VirtReg) {
549 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg)))
555 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) {
557 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg));
566 /// DBG_VALUEs with \p VirtReg operands with the stack slot.
568 Register VirtReg, MCPhysReg AssignedReg, bool Kill,
570 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) << " in "
572 int FI = getStackSpaceFor(VirtReg);
575 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
577 VirtReg);
585 SmallVectorImpl<MachineOperand *> &LRIDbgOperands = LiveDbgValueMap[VirtReg];
629 Register VirtReg, MCPhysReg PhysReg) {
630 LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into "
632 int FI = getStackSpaceFor(VirtReg);
633 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
634 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg);
702 reload(MBB.begin(), LR.VirtReg, PhysReg);
704 reload(InsertBefore, LR.VirtReg, PhysReg);
733 switch (unsigned VirtReg = RegUnitStates[Unit]) {
735 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
739 reload(ReloadBefore, VirtReg, LRI->PhysReg);
762 switch (unsigned VirtReg = RegUnitStates[FirstUnit]) {
771 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
773 LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n');
787 switch (unsigned VirtReg = RegUnitStates[Unit]) {
795 bool SureSpill = StackSlotForVirtReg[VirtReg] != -1 ||
796 findLiveVirtReg(VirtReg)->LiveOut;
805 Register VirtReg,
807 auto UDBGValIter = DanglingDbgValues.find(VirtReg);
814 if (!DbgValue->hasDebugOperandForReg(VirtReg))
830 for (MachineOperand &MO : DbgValue->getDebugOperandsForReg(VirtReg)) {
840 /// proper container for VirtReg now. The physical register must not be used
844 Register VirtReg = LR.VirtReg;
845 LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to "
850 setPhysRegState(PhysReg, VirtReg);
852 assignDanglingDebugValues(AtMI, VirtReg, PhysReg);
873 /// Check if any of \p VirtReg's definitions is a copy. If it is follow the
876 Register RegAllocFastImpl::traceCopies(Register VirtReg) const {
879 for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) {
893 /// Allocates a physical register for VirtReg.
896 const Register VirtReg = LR.VirtReg;
899 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
900 LLVM_DEBUG(dbgs() << "Search register for " << printReg(VirtReg)
922 Register Hint1 = traceCopies(VirtReg);
980 Register VirtReg = MO.getReg();
981 assert(VirtReg.isVirtual() && "Expected virtreg");
982 if (!shouldAllocateRegister(VirtReg))
985 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
990 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
1018 Register VirtReg) {
1019 if (!shouldAllocateRegister(VirtReg))
1021 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
1043 return defineVirtReg(MI, OpNum, VirtReg, true);
1046 /// Allocates a register for VirtReg definition. Typically the register is
1054 Register VirtReg, bool LookAtPhysRegUses) {
1055 assert(VirtReg.isVirtual() && "Not a virtual register");
1056 if (!shouldAllocateRegister(VirtReg))
1061 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
1064 if (mayLiveOut(VirtReg)) {
1077 LLVM_DEBUG(dbgs() << "In def of " << printReg(VirtReg, TRI)
1090 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
1095 int FI = StackSlotForVirtReg[VirtReg];
1096 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
1101 &RC, TRI, VirtReg);
1114 BundleVirtRegsMap[VirtReg] = PhysReg;
1120 /// Allocates a register for a VirtReg use.
1123 Register VirtReg) {
1124 assert(VirtReg.isVirtual() && "Not a virtual register");
1125 if (!shouldAllocateRegister(VirtReg))
1129 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
1132 if (mayLiveOut(VirtReg)) {
1163 BundleVirtRegsMap[VirtReg] = LRI->PhysReg;
1262 switch (unsigned VirtReg = RegUnitStates[Unit]) {
1271 dbgs() << ' ' << printRegUnit(Unit, TRI) << '=' << printReg(VirtReg);
1272 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg);
1290 Register VirtReg = LR.VirtReg;
1291 assert(VirtReg.isVirtual() && "Bad map key");
1296 assert(RegUnitStates[Unit] == VirtReg && "inverse map valid");