Lines Matching defs:PhysReg
203 MCPhysReg PhysReg = 0; ///< Currently held here.
279 void setPhysRegState(MCRegister PhysReg, unsigned NewState);
280 bool isPhysRegFree(MCPhysReg PhysReg) const;
283 void markRegUsedInInstr(MCPhysReg PhysReg) {
284 for (MCRegUnit Unit : TRI->regunits(PhysReg))
289 bool isClobberedByRegMasks(MCPhysReg PhysReg) const {
290 return llvm::any_of(RegMasks, [PhysReg](const uint32_t *Mask) {
291 return MachineOperand::clobbersPhysReg(Mask, PhysReg);
296 bool isRegUsedInInstr(MCPhysReg PhysReg, bool LookAtPhysRegUses) const {
297 if (LookAtPhysRegUses && isClobberedByRegMasks(PhysReg))
299 for (MCRegUnit Unit : TRI->regunits(PhysReg))
307 void markPhysRegUsedInInstr(MCPhysReg PhysReg) {
308 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
315 void unmarkRegUsedInInstr(MCPhysReg PhysReg) {
316 for (MCRegUnit Unit : TRI->regunits(PhysReg))
344 bool usePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
345 bool definePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
346 bool displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg);
347 void freePhysReg(MCPhysReg PhysReg);
349 unsigned calcSpillCost(MCPhysReg PhysReg) const;
359 void assignVirtToPhysReg(MachineInstr &MI, LiveReg &, MCPhysReg PhysReg);
379 bool setPhysReg(MachineInstr &MI, MachineOperand &MO, MCPhysReg PhysReg);
389 MCPhysReg PhysReg);
452 void RegAllocFastImpl::setPhysRegState(MCRegister PhysReg, unsigned NewState) {
453 for (MCRegUnit Unit : TRI->regunits(PhysReg))
457 bool RegAllocFastImpl::isPhysRegFree(MCPhysReg PhysReg) const {
458 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
627 /// Insert reload instruction for \p PhysReg before \p Before.
629 Register VirtReg, MCPhysReg PhysReg) {
631 << printReg(PhysReg, TRI) << '\n');
634 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg);
674 MCRegister Reg = P.PhysReg;
687 MCPhysReg PhysReg = LR.PhysReg;
688 if (PhysReg == 0 || LR.Error)
691 MCRegUnit FirstUnit = *TRI->regunits(PhysReg).begin();
698 if (PrologLiveIns.count(PhysReg)) {
702 reload(MBB.begin(), LR.VirtReg, PhysReg);
704 reload(InsertBefore, LR.VirtReg, PhysReg);
726 /// Mark PhysReg as reserved or free after spilling any virtregs. This is very
729 bool RegAllocFastImpl::displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg) {
732 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
739 reload(ReloadBefore, VirtReg, LRI->PhysReg);
741 setPhysRegState(LRI->PhysReg, regFree);
742 LRI->PhysReg = 0;
758 void RegAllocFastImpl::freePhysReg(MCPhysReg PhysReg) {
759 LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':');
761 MCRegUnit FirstUnit = *TRI->regunits(PhysReg).begin();
768 setPhysRegState(PhysReg, regFree);
774 setPhysRegState(LRI->PhysReg, regFree);
775 LRI->PhysReg = 0;
781 /// Return the cost of spilling clearing out PhysReg and aliases so it is free
782 /// for allocation. Returns 0 when PhysReg is free or disabled with all aliases
784 /// \returns spillImpossible when PhysReg or an alias can't be spilled.
785 unsigned RegAllocFastImpl::calcSpillCost(MCPhysReg PhysReg) const {
786 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
792 << printReg(PhysReg, TRI) << '\n');
839 /// This method updates local state so that we know that PhysReg is the
843 MCPhysReg PhysReg) {
846 << printReg(PhysReg, TRI) << '\n');
847 assert(LR.PhysReg == 0 && "Already assigned a physreg");
848 assert(PhysReg != 0 && "Trying to assign no register");
849 LR.PhysReg = PhysReg;
850 setPhysRegState(PhysReg, VirtReg);
852 assignDanglingDebugValues(AtMI, VirtReg, PhysReg);
897 assert(LR.PhysReg == 0);
942 for (MCPhysReg PhysReg : AllocationOrder) {
943 LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << ' ');
944 if (isRegUsedInInstr(PhysReg, LookAtPhysRegUses)) {
949 unsigned Cost = calcSpillCost(PhysReg);
953 assignVirtToPhysReg(MI, LR, PhysReg);
957 if (PhysReg == Hint0 || PhysReg == Hint1)
961 BestReg = PhysReg;
969 LR.PhysReg = getErrorAssignment(LR, MI, RC);
986 MCPhysReg PhysReg;
987 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
988 PhysReg = LRI->PhysReg;
998 PhysReg = getErrorAssignment(*LRI, *MO.getParent(), RC);
1001 PhysReg = AllocationOrder.front();
1006 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx);
1009 MO.setReg(PhysReg);
1023 MCPhysReg PrevReg = LRI->PhysReg;
1028 LRI->PhysReg = 0;
1032 LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to "
1036 .addReg(LRI->PhysReg, llvm::RegState::Kill);
1072 if (LRI->PhysReg == 0) {
1075 assert((!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) || LRI->Error) &&
1079 << printReg(LRI->PhysReg, TRI) << '\n');
1082 MCPhysReg PhysReg = LRI->PhysReg;
1090 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
1100 TII->storeRegToStackSlot(*Succ, Succ->begin(), PhysReg, Kill, FI,
1103 Succ->addLiveIn(PhysReg);
1114 BundleVirtRegsMap[VirtReg] = PhysReg;
1116 markRegUsedInInstr(PhysReg);
1117 return setPhysReg(MI, MO, PhysReg);
1144 if (LRI->PhysReg == 0) {
1163 BundleVirtRegsMap[VirtReg] = LRI->PhysReg;
1165 markRegUsedInInstr(LRI->PhysReg);
1166 return setPhysReg(MI, MO, LRI->PhysReg);
1217 /// Changes operand OpNum in MI the refer the PhysReg, considering subregs.
1220 MCPhysReg PhysReg) {
1222 MO.setReg(PhysReg);
1228 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister());
1239 MI.addRegisterKilled(PhysReg, TRI, true);
1248 MI.addRegisterDead(PhysReg, TRI, true);
1250 MI.addRegisterDefined(PhysReg, TRI);
1282 assert(TRI->hasRegUnit(I->PhysReg, Unit) && "inverse mapping present");
1292 MCPhysReg PhysReg = LR.PhysReg;
1293 if (PhysReg != 0) {
1294 assert(Register::isPhysicalRegister(PhysReg) && "mapped to physreg");
1295 for (MCRegUnit Unit : TRI->regunits(PhysReg)) {
1576 MCPhysReg PhysReg = LR.PhysReg;
1577 if (PhysReg != 0 && isClobberedByRegMasks(PhysReg))
1578 displacePhysReg(MI, PhysReg);
1708 if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
1711 setPhysReg(MI, *RegMO, LRI->PhysReg);
1754 setPhysRegState(LiveReg.PhysReg, regPreAssigned);