Lines Matching defs:LRI

735       LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
736       assert(LRI != LiveVirtRegs.end() && "datastructures in sync");
739       reload(ReloadBefore, VirtReg, LRI->PhysReg);
741       setPhysRegState(LRI->PhysReg, regFree);
742       LRI->PhysReg = 0;
743       LRI->Reloaded = true;
771     LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
772     assert(LRI != LiveVirtRegs.end());
773     LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n');
774     setPhysRegState(LRI->PhysReg, regFree);
775     LRI->PhysReg = 0;
985   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
987   if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
988     PhysReg = LRI->PhysReg;
998       PhysReg = getErrorAssignment(*LRI, *MO.getParent(), RC);
999       LRI->Error = true;
1021   LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg);
1022   if (LRI != LiveVirtRegs.end()) {
1023     MCPhysReg PrevReg = LRI->PhysReg;
1028       LRI->PhysReg = 0;
1029       allocVirtReg(MI, *LRI, 0, true);
1032       LLVM_DEBUG(dbgs() << "Copy " << printReg(LRI->PhysReg, TRI) << " to "
1036           .addReg(LRI->PhysReg, llvm::RegState::Kill);
1040       LRI->LastUse = &MI;
1059   LiveRegMap::iterator LRI;
1061   std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
1065         LRI->LiveOut = true;
1072   if (LRI->PhysReg == 0) {
1073     allocVirtReg(MI, *LRI, 0, LookAtPhysRegUses);
1075     assert((!isRegUsedInInstr(LRI->PhysReg, LookAtPhysRegUses) || LRI->Error) &&
1079                       << printReg(LRI->PhysReg, TRI) << '\n');
1082   MCPhysReg PhysReg = LRI->PhysReg;
1083   if (LRI->Reloaded || LRI->LiveOut) {
1087       LLVM_DEBUG(dbgs() << "Spill Reason: LO: " << LRI->LiveOut
1088                         << " RL: " << LRI->Reloaded << '\n');
1089       bool Kill = LRI->LastUse == nullptr;
1090       spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut);
1108       LRI->LastUse = nullptr;
1110     LRI->LiveOut = false;
1111     LRI->Reloaded = false;
1127   LiveRegMap::iterator LRI;
1129   std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg));
1133         LRI->LiveOut = true;
1140     assert((!MO.isKill() || LRI->LastUse == &MI) && "Invalid kill flag");
1144   if (LRI->PhysReg == 0) {
1157     allocVirtReg(MI, *LRI, Hint, false);
1160   LRI->LastUse = &MI;
1163     BundleVirtRegsMap[VirtReg] = LRI->PhysReg;
1165   markRegUsedInInstr(LRI->PhysReg);
1166   return setPhysReg(MI, MO, LRI->PhysReg);
1703     LiveRegMap::iterator LRI = findLiveVirtReg(Reg);
1708     if (LRI != LiveVirtRegs.end() && LRI->PhysReg) {
1711         setPhysReg(MI, *RegMO, LRI->PhysReg);