Lines Matching defs:DefInstr

151   MachineInstr *DefInstr = nullptr;
154     DefInstr = MRI->getUniqueVRegDef(MO.getReg());
155   return DefInstr;
225         MachineInstr *DefInstr = InsInstrs[II->second];
226         assert(DefInstr &&
230             DefInstr->findRegisterDefOperandIdx(MO.getReg(), /*TRI=*/nullptr);
233         LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx,
236         MachineInstr *DefInstr = getOperandDef(MO);
237         if (DefInstr && (TII->getMachineCombinerTraceStrategy() !=
239                          DefInstr->getParent() == &MBB)) {
240           DepthOp = BlockTrace.getInstrCycles(*DefInstr).Depth;
241           if (!isTransientMI(DefInstr))
243                 DefInstr,
244                 DefInstr->findRegisterDefOperandIdx(MO.getReg(),