Lines Matching defs:Op0

184 void MachineIRBuilder::validateUnaryOp(const LLT Res, const LLT Op0) {
186 assert((Res == Op0) && "type mismatch");
189 void MachineIRBuilder::validateBinaryOp(const LLT Res, const LLT Op0,
192 assert((Res == Op0 && Res == Op1) && "type mismatch");
195 void MachineIRBuilder::validateShiftOp(const LLT Res, const LLT Op0,
198 assert((Res == Op0) && "type mismatch");
202 MachineIRBuilder::buildPtrAdd(const DstOp &Res, const SrcOp &Op0,
205 Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
208 return buildInstr(TargetOpcode::G_PTR_ADD, {Res}, {Op0, Op1}, Flags);
212 MachineIRBuilder::materializePtrAdd(Register &Res, Register Op0,
218 Res = Op0;
222 Res = getMRI()->createGenericVirtualRegister(getMRI()->getType(Op0));
224 return buildPtrAdd(Res, Op0, Cst.getReg(0));
228 const SrcOp &Op0,
234 return buildPtrMask(Res, Op0, MaskReg);
239 const SrcOp &Op0) {
241 LLT Op0Ty = Op0.getLLTTy(*getMRI());
250 "Op0 has more elements");
251 auto Unmerge = buildUnmerge(Op0Ty.getElementType(), Op0);
257 "Op0 has more size");
258 Regs.push_back(Op0.getReg());
270 const SrcOp &Op0) {
272 LLT Op0Ty = Op0.getLLTTy(*getMRI());
281 "Op0 has fewer elements");
283 auto Unmerge = buildUnmerge(Op0Ty.getElementType(), Op0);
922 const SrcOp &Op0,
925 return buildInstr(TargetOpcode::G_ICMP, Res, {Pred, Op0, Op1}, Flags);
930 const SrcOp &Op0,
934 return buildInstr(TargetOpcode::G_FCMP, Res, {Pred, Op0, Op1}, Flags);
938 const SrcOp &Op0,
940 return buildInstr(TargetOpcode::G_SCMP, Res, {Op0, Op1});
944 const SrcOp &Op0,
946 return buildInstr(TargetOpcode::G_UCMP, Res, {Op0, Op1});
951 const SrcOp &Op0, const SrcOp &Op1,
954 return buildInstr(TargetOpcode::G_SELECT, {Res}, {Tst, Op0, Op1}, Flags);