Lines Matching defs:Addr

403                                        Register Addr, Register AddrDisc) {
406   MIB.addUse(Addr);
424 MachineIRBuilder::buildLoad(const DstOp &Dst, const SrcOp &Addr,
434   return buildLoad(Dst, Addr, *MMO);
439                                                      const SrcOp &Addr,
442   assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
446   Addr.addSrcToMIB(MIB);
469                                                  const SrcOp &Addr,
472   assert(Addr.getLLTTy(*getMRI()).isPointer() && "invalid operand type");
476   Addr.addSrcToMIB(MIB);
482 MachineIRBuilder::buildStore(const SrcOp &Val, const SrcOp &Addr,
492   return buildStore(Val, Addr, *MMO);
985     const DstOp &OldValRes, const DstOp &SuccessRes, const SrcOp &Addr,
990   LLT AddrTy = Addr.getLLTTy(*getMRI());
1005   Addr.addSrcToMIB(MIB);
1013 MachineIRBuilder::buildAtomicCmpXchg(const DstOp &OldValRes, const SrcOp &Addr,
1018   LLT AddrTy = Addr.getLLTTy(*getMRI());
1031   Addr.addSrcToMIB(MIB);
1040   const SrcOp &Addr, const SrcOp &Val,
1045   LLT AddrTy = Addr.getLLTTy(*getMRI());
1055   Addr.addSrcToMIB(MIB);
1062 MachineIRBuilder::buildAtomicRMWXchg(Register OldValRes, Register Addr,
1064   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XCHG, OldValRes, Addr, Val,
1068 MachineIRBuilder::buildAtomicRMWAdd(Register OldValRes, Register Addr,
1070   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_ADD, OldValRes, Addr, Val,
1074 MachineIRBuilder::buildAtomicRMWSub(Register OldValRes, Register Addr,
1076   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_SUB, OldValRes, Addr, Val,
1080 MachineIRBuilder::buildAtomicRMWAnd(Register OldValRes, Register Addr,
1082   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_AND, OldValRes, Addr, Val,
1086 MachineIRBuilder::buildAtomicRMWNand(Register OldValRes, Register Addr,
1088   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_NAND, OldValRes, Addr, Val,
1092                                                        Register Addr,
1095   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_OR, OldValRes, Addr, Val,
1099 MachineIRBuilder::buildAtomicRMWXor(Register OldValRes, Register Addr,
1101   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_XOR, OldValRes, Addr, Val,
1105 MachineIRBuilder::buildAtomicRMWMax(Register OldValRes, Register Addr,
1107   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MAX, OldValRes, Addr, Val,
1111 MachineIRBuilder::buildAtomicRMWMin(Register OldValRes, Register Addr,
1113   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_MIN, OldValRes, Addr, Val,
1117 MachineIRBuilder::buildAtomicRMWUmax(Register OldValRes, Register Addr,
1119   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMAX, OldValRes, Addr, Val,
1123 MachineIRBuilder::buildAtomicRMWUmin(Register OldValRes, Register Addr,
1125   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_UMIN, OldValRes, Addr, Val,
1131   const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1133   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FADD, OldValRes, Addr, Val,
1138 MachineIRBuilder::buildAtomicRMWFSub(const DstOp &OldValRes, const SrcOp &Addr, const SrcOp &Val,
1140   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FSUB, OldValRes, Addr, Val,
1145 MachineIRBuilder::buildAtomicRMWFMax(const DstOp &OldValRes, const SrcOp &Addr,
1147   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FMAX, OldValRes, Addr, Val,
1152 MachineIRBuilder::buildAtomicRMWFMin(const DstOp &OldValRes, const SrcOp &Addr,
1154   return buildAtomicRMW(TargetOpcode::G_ATOMICRMW_FMIN, OldValRes, Addr, Val,
1165 MachineInstrBuilder MachineIRBuilder::buildPrefetch(const SrcOp &Addr,
1171   Addr.addSrcToMIB(MIB);