Lines Matching defs:RegsToVisit

3794   SmallVector<Register, 8> RegsToVisit;
3817       RegsToVisit.push_back(OrLHS);
3821       RegsToVisit.push_back(OrRHS);
3826   if (RegsToVisit.empty() || RegsToVisit.size() % 2 != 0)
3828   return RegsToVisit;
3869     const SmallVector<Register, 8> &RegsToVisit,
3872   // Each load found for the pattern. There should be one for each RegsToVisit.
3902   for (auto Reg : RegsToVisit) {
3974   assert(Loads.size() == RegsToVisit.size() &&
4028   auto RegsToVisit = findCandidatesForLoadOrCombine(&MI);
4029   if (!RegsToVisit)
4035   const unsigned NarrowMemSizeInBits = WideMemSizeInBits / RegsToVisit->size();
4050       MemOffset2Idx, *RegsToVisit, NarrowMemSizeInBits);