Lines Matching defs:TReg

114     unsigned TReg = 0, FReg = 0;
115     // Latencies from Cond+Branch, TReg, and FReg to DstReg.
521         PI.TReg = PI.PHI->getOperand(i).getReg();
525     assert(Register::isVirtualRegister(PI.TReg) && "Bad PHI");
530                               PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles,
566                          const TargetInstrInfo *TII, Register TReg,
568   if (TReg == FReg)
571   if (!TReg.isVirtual() || !FReg.isVirtual())
574   const MachineInstr *TDef = MRI.getUniqueVRegDef(TReg);
602   int TIdx = TDef->findRegisterDefOperandIdx(TReg, /*TRI=*/nullptr);
623     if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) {
627           .addReg(PI.TReg);
629       TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg,
651     if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) {
654       DstReg = PI.TReg;
659                          DstReg, Cond, PI.TReg, PI.FReg);