Lines Matching defs:FReg

114     unsigned TReg = 0, FReg = 0;
115     // Latencies from Cond+Branch, TReg, and FReg to DstReg.
523         PI.FReg = PI.PHI->getOperand(i).getReg();
526     assert(Register::isVirtualRegister(PI.FReg) && "Bad PHI");
530                               PI.TReg, PI.FReg, PI.CondCycles, PI.TCycles,
567                          Register FReg) {
568   if (TReg == FReg)
571   if (!TReg.isVirtual() || !FReg.isVirtual())
575   const MachineInstr *FDef = MRI.getUniqueVRegDef(FReg);
603   int FIdx = FDef->findRegisterDefOperandIdx(FReg, /*TRI=*/nullptr);
623     if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) {
630                         PI.FReg);
651     if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) {
659                          DstReg, Cond, PI.TReg, PI.FReg);