Lines Matching defs:Reg

70         unsigned Reg = (*AI).id();
71         Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
72         KillIndices[Reg] = BBSize;
73         DefIndices[Reg] = ~0u;
84     unsigned Reg = *I;
85     if (!IsReturnBlock && !Pristine.test(Reg))
88       unsigned Reg = (*AI).id();
89       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
90       KillIndices[Reg] = BBSize;
91       DefIndices[Reg] = ~0u;
114   for (unsigned Reg = 1; Reg != TRI->getNumRegs(); ++Reg) {
115     if (KillIndices[Reg] != ~0u) {
116       // If Reg is currently live, then mark that it can't be renamed as
119       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
120       KillIndices[Reg] = Count;
121     } else if (DefIndices[Reg] < InsertPosIndex && DefIndices[Reg] >= Count) {
126       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
130       DefIndices[Reg] = InsertPosIndex;
184     Register Reg = MO.getReg();
185     if (Reg == 0) continue;
193     if (!Classes[Reg] && NewRC)
194       Classes[Reg] = NewRC;
195     else if (!NewRC || Classes[Reg] != NewRC)
196       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
199     for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
206         Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
211     if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
212       RegRefs.insert(std::make_pair(Reg, &MO));
215       if (!KeepRegs.test(Reg)) {
216         for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
225     Register Reg = MO.getReg();
226     if (!Reg.isValid())
228     // If this reg is tied and live (Classes[Reg] is set to -1), we can't change
239         Classes[Reg] == reinterpret_cast<TargetRegisterClass *>(-1)) {
240       for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) {
243       for (MCPhysReg SuperReg : TRI->superregs(Reg)) {
280       Register Reg = MO.getReg();
281       if (Reg == 0) continue;
290       bool Keep = KeepRegs.test(Reg);
294       for (MCPhysReg SubregReg : TRI->subregs_inclusive(Reg)) {
303       for (MCPhysReg SR : TRI->superregs(Reg))
310     Register Reg = MO.getReg();
311     if (Reg == 0) continue;
320     if (!Classes[Reg] && NewRC)
321       Classes[Reg] = NewRC;
322     else if (!NewRC || Classes[Reg] != NewRC)
323       Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
325     RegRefs.insert(std::make_pair(Reg, &MO));
329     for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
466     for (unsigned Reg = 1; Reg < TRI->getNumRegs(); ++Reg) {
467       if (KillIndices[Reg] == ~0u)
468         LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
614         Register Reg = MO.getReg();
615         if (Reg == 0) continue;
616         if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
620         if (MO.isDef() && Reg != AntiDepReg)
621           ForbidRegs.push_back(Reg);