Lines Matching defs:NewReg

340 // be replaced by NewReg. Return true if any of their parent instructions may
345 // the two-address instruction also defines NewReg, as may happen with
349 // both NewReg and AntiDepReg covers it.
353 unsigned NewReg) {
358 // operands, in case they may be assigned to NewReg. In this case antidep
363 // Handle cases in which this instruction defines NewReg.
366 if (CheckOper.isRegMask() && CheckOper.clobbersPhysReg(NewReg))
370 CheckOper.getReg() != NewReg)
373 // Don't allow the instruction to define NewReg and AntiDepReg.
379 // NewReg.
383 // Don't allow inline asm to define NewReg at all. Who knows what it's
400 for (unsigned NewReg : Order) {
402 if (NewReg == AntiDepReg) continue;
406 if (NewReg == LastNewReg) continue;
407 // If any instructions that define AntiDepReg also define the NewReg, it's
410 if (isNewRegClobberedByRefs(RegRefBegin, RegRefEnd, NewReg)) continue;
411 // If NewReg is dead and NewReg's most recent def is not before
412 // AntiDepReg's kill, it's safe to replace AntiDepReg with NewReg.
415 assert(((KillIndices[NewReg] == ~0u) != (DefIndices[NewReg] == ~0u))
416 && "Kill and Def maps aren't consistent for NewReg!");
417 if (KillIndices[NewReg] != ~0u ||
418 Classes[NewReg] == reinterpret_cast<TargetRegisterClass *>(-1) ||
419 KillIndices[AntiDepReg] > DefIndices[NewReg])
421 // If NewReg overlaps any of the forbidden registers, we can't use it.
424 if (TRI->regsOverlap(NewReg, R)) {
429 return NewReg;
642 if (unsigned NewReg = findSuitableFreeRegister(Range.first, Range.second,
649 << " using " << printReg(NewReg, TRI) << "!\n");
655 Q->second->setReg(NewReg);
662 AntiDepReg, NewReg);
668 Classes[NewReg] = Classes[AntiDepReg];
669 DefIndices[NewReg] = DefIndices[AntiDepReg];
670 KillIndices[NewReg] = KillIndices[AntiDepReg];
671 assert(((KillIndices[NewReg] == ~0u) !=
672 (DefIndices[NewReg] == ~0u)) &&
673 "Kill and Def maps aren't consistent for NewReg!");
683 LastNewReg[AntiDepReg] = NewReg;