Lines Matching defs:Reg
70 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
71 unsigned Node = GroupNodeIndices[Reg];
83 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
84 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
85 Regs.push_back(Reg);
91 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
104 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) {
105 // Create a new GroupNode for Reg. Reg's existing GroupNode must
110 GroupNodeIndices[Reg] = idx;
114 bool AggressiveAntiDepState::IsLive(unsigned Reg) {
117 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
158 unsigned Reg = *AI;
159 State->UnionGroups(Reg, 0);
160 KillIndices[Reg] = BB->size();
161 DefIndices[Reg] = ~0u;
172 unsigned Reg = *I;
173 if (!IsReturnBlock && !Pristine.test(Reg))
175 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
203 for (unsigned Reg = 1; Reg != TRI->getNumRegs(); ++Reg) {
204 // If Reg is current live, then mark that it can't be renamed as
210 if (State->IsLive(Reg)) {
211 LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs()
212 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)
214 State->UnionGroups(Reg, 0);
215 } else if ((DefIndices[Reg] < InsertPosIndex)
216 && (DefIndices[Reg] >= Count)) {
217 DefIndices[Reg] = Count;
228 Register Reg = MO.getReg();
229 if (Reg == 0)
234 Op = MI.findRegisterUseOperand(Reg, /*TRI=*/nullptr, true);
236 Op = MI.findRegisterDefOperand(Reg, /*TRI=*/nullptr);
248 const Register Reg = MO.getReg();
249 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
291 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
304 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
305 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
310 if (!State->IsLive(Reg)) {
311 KillIndices[Reg] = KillIdx;
312 DefIndices[Reg] = ~0u;
313 RegRefs.erase(Reg);
314 State->LeaveGroup(Reg);
316 dbgs() << header << printReg(Reg, TRI);
319 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
324 for (MCPhysReg SubregReg : TRI->subregs(Reg)) {
331 dbgs() << header << printReg(Reg, TRI);
355 Register Reg = MO.getReg();
356 if (Reg == 0) continue;
358 HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
365 Register Reg = MO.getReg();
366 if (Reg == 0) continue;
368 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
369 << State->GetGroup(Reg));
378 LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
379 State->UnionGroups(Reg, 0);
383 // partially defined here, so group those aliases with Reg.
384 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
387 State->UnionGroups(Reg, AliasReg);
388 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via "
398 RegRefs.insert(std::make_pair(Reg, RR));
406 Register Reg = MO.getReg();
407 if (Reg == 0) continue;
409 if (MI.isKill() || (PassthruRegs.count(Reg) != 0))
412 // Update def for Reg and aliases.
413 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
420 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
459 Register Reg = MO.getReg();
460 if (Reg == 0) continue;
462 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
463 << State->GetGroup(Reg));
468 HandleLastUse(Reg, Count, "(last-use)");
471 LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
472 State->UnionGroups(Reg, 0);
480 RegRefs.insert(std::make_pair(Reg, RR));
493 Register Reg = MO.getReg();
494 if (Reg == 0) continue;
497 LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI));
498 State->UnionGroups(FirstReg, Reg);
500 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
501 FirstReg = Reg;
509 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
513 // Check all references that need rewriting for Reg. For each, use
516 for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) {
556 for (unsigned Reg : Regs) {
557 // If Reg has any references, then collect possible rename regs
558 if (RegRefs.count(Reg) > 0) {
559 LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
561 BitVector &BV = RenameRegisterMap[Reg];
563 BV = GetRenameRegisters(Reg);
575 for (unsigned Reg : Regs) {
576 if (Reg == SuperReg) continue;
577 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
636 for (unsigned Reg : Regs) {
638 if (Reg == SuperReg) {
641 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
648 // Check if Reg can be renamed to NewReg.
649 if (!RenameRegisterMap[Reg].test(NewReg)) {
655 // Regs's kill, it's safe to replace Reg with NewReg. We
658 if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
666 (KillIndices[Reg] > DefIndices[AliasReg])) {
677 // We cannot rename 'Reg' to 'NewReg' if one of the uses of 'Reg' also
679 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
691 // Also, we cannot rename 'Reg' to 'NewReg' if the instruction defining
692 // 'Reg' is an early-clobber define and that instruction also uses
694 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) {
705 // Record that 'Reg' can be renamed to 'NewReg'.
706 RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
771 for (unsigned Reg = 1; Reg < TRI->getNumRegs(); ++Reg) {
772 if (!State->IsLive(Reg))
773 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));