Lines Matching +full:- +full:- +full:issue +full:- +full:number
1 //===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the target-independent scheduling interfaces which should
14 // 2. Scheduler Read/Write resources for simple per-opcode cost model.
21 // (2) A per-operand machine model can be implemented in any
24 // A. Associate per-operand SchedReadWrite types with Instructions by
31 // per-operand SchedReadWrite types. Unlike method A, these types may
45 // a machine-independent SchedReadWrite type to map to a sequence of
46 // machine-dependent types.
48 // (3) A per-pipeline-stage machine model can be implemented by providing
50 //===----------------------------------------------------------------------===//
68 // properties are defined in MCSchedModel. A value of "-1" in the
77 int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
78 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
79 int LoopMicroOpBufferSize = -1; // Max micro-ops that can be buffered for
81 int LoadLatency = -1; // Cycles for loads to access the cache.
82 int HighLatency = -1; // Approximation of cycles for "high latency" ops.
83 int MispredictPenalty = -1; // Extra cycles for a mispredicted branch.
85 // Per-cycle resources tables.
136 // Define a number of interchangeable processor resources. NumUnits
144 // out-of-order engine. Buffered resources may be held for multiple
147 // changes this to an in-order issue/dispatch resource. In this case,
149 // issues in-order, forcing a stall whenever a subsequent instruction
150 // requires the same resource until the number of ReleaseAtCycles
152 // an in-order latency resource. In this case, the scheduler models
156 // Examples (all assume an out-of-order engine):
158 // Use BufferSize = -1 for "issue ports" fed by a unified reservation
164 // Use BufferSize = 0 for resources that force "dispatch/issue
165 // groups". (Different processors define dispath/issue
166 // differently. Here we refer to stage between decoding into micro-ops
168 // is sufficient to limit dispatch/issue groups. However, some
172 // Use BufferSize = 1 for in-order execution units. This is used for
173 // an in-order pipeline within an out-of-order core where scheduling
174 // dependent operations back-to-back is guaranteed to cause a
175 // bubble. e.g. Cortex-a9 floating-point.
177 // Use BufferSize > 1 for out-of-order executions units with a
181 // To model both dispatch/issue groups and in-order execution units,
185 // SchedModel ties these units to a processor for any stand-alone defs
191 int BufferSize = -1;
195 // Subtargets typically define processor resource kind and number of
203 int BufferSize = -1;
210 // List the per-operand types that map to the machine model of an
217 // two-address instruction could have two tied operands or single
267 // Allow a processor to mark some scheduling classes as single-issue.
270 // An instruction is allowed to retire out-of-order if RetireOOO is
272 // MCA for in-order subtargets, and is ignored for other targets.
289 // Optionally, ReleaseAtCycles indicates the number of cycles the
298 // By default, each SchedWrite takes one micro-op, which is counted
300 // write multiple registers with a single micro-op, the subtarget
301 // should define one of the writes to be zero micro-ops. If a
302 // subtarget requires multiple micro-ops to write a single result, it
306 // instruction's list of writers beyond the number of "def"
307 // operands. The scheduler assumes that all micro-ops must be
308 // dispatched in the same cycle. These micro-ops may be required to
335 // effectively increases latency, which may be used for cross-domain
340 // indicate operands that are always read this number of Cycles later
342 // to issue earlier relative to the writer.
376 // if-statement's expression. Available variables are MI, SchedModel,
387 // MCSchedPredicate, this is the default scheduling case used by llvm-mca.
418 // per-operand instead of the usual sequential writes feeding a single
456 // Alias a target-defined SchedReadWrite to a processor specific
473 // - The set of registers that can be renamed.
474 // - The number of physical registers which can be used for register renaming
476 // - The cost of a register rename.
477 // - The set of registers that allow move elimination.
478 // - The maximum number of moves that can be eliminated every cycle.
479 // - Whether move elimination is limited to register moves whose input
482 // The cost of a rename is the number of physical registers allocated by the
496 // A sub-register V of register R is implicitly part of the same register file.
509 // There is also no penalty for writes that "clear the content a super-register"
510 // (see MC/MCInstrAnalysis.h - method MCInstrAnalysis::clearsSuperRegisters()).
511 // On x86-64, 32-bit GPR writes implicitly zero the upper half of the underlying
515 // TODO: This implementation assumes that there is no limit in the number of
524 // partial write is combined with the previous super-register definition. We
530 // to the number of moves that can be eliminated by this register file.
541 // - MI is a move elimination candidate.
542 // - The destination register is from a register class that allows move
544 // - Constraints on the move kind, and the maximum number of moves that can be
561 // the maximum number of opcodes that can be retired every cycle.
562 // A value less-than-or-equal-to zero for field 'ReorderBufferSize' means: "the
563 // size is unknown". The idea is that external tools can fall-back to using
566 // restrictions on the number of instructions retired per cycle".