Lines Matching +full:- +full:- +full:issue +full:- +full:number
1 //===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
36 unsigned NumUnits; // Number of resource of this kind
39 // Number of resources that may be buffered.
42 // cycle after dispatch. This should be used for out-of-order cpus when
47 // fixed number of cycles after dispatch. If a resource is unbuffered, then
49 // in the same cycle. This is for in-order cpus, or the in-order portion of
50 // an out-of-order cpus.
53 // If the resource has sub-units, a pointer to the first element of an array
55 // nullptr if the resource does not have sub-units.
65 /// particular scheduling class for the specified number of cycles.
85 /// index. -1 indicates an invalid latency. Heuristics would typically consider
98 /// Specify the number of cycles allowed after instruction issue before a
122 static const unsigned short InvalidNumMicroOps = (1U << 13) - 1;
123 static const unsigned short VariantNumMicroOps = InvalidNumMicroOps - 1;
147 /// Specify the cost of a register definition in terms of number of physical
149 /// natively supports 128-bit data types, and operations on 256-bit registers
165 /// FIXME: this struct can be extended to provide information about the number
167 /// 'NumPhysRegs' means: this register file has an unbounded number of physical
175 // A value of zero means: there is no limit in the number of moves that can be
187 /// external tools like llvm-mca to improve the quality of the peformance
192 // Number of instructions retired per cycle.
214 /// an abstract machine model. A real micro-architecture has a number of
215 /// buffers, queues, and stages. Declaring that a given machine-independent
222 /// The abstract pipeline is built around the notion of an "issue point". This
230 /// a processor resource when writing data for a number of abstract
237 /// A note on out-of-order execution and, more generally, instruction
238 /// buffers. Part of the CPU pipeline is always in-order. The issue point, which
240 /// in-order part of the pipeline. Other parts of the pipeline are sometimes
245 /// The LLVM machine model distinguishes between in-order constraints and
246 /// out-of-order constraints so that the target's scheduling strategy can apply
247 /// appropriate heuristics. For a well-balanced CPU pipeline, out-of-order
250 /// out-of-order resources is not directly reflected in the number of cycles
252 /// instructions. In other words, out-of-order resources don't directly increase
257 // IssueWidth is the maximum number of instructions that may be scheduled in
258 // the same per-cycle group. This is meant to be a hard in-order constraint
260 // IssueWidth micro-ops can ever be scheduled in a particular cycle.
263 // decoder (after micro-op expansion) and the out-of-order reservation
264 // stations or the decoder bandwidth itself. If the total number of
267 // out-of-order processor resource.
271 // MicroOpBufferSize is the number of micro-ops that the processor may buffer
272 // for out-of-order execution.
279 // whether they are ready in this cycle. Latency still causes issue stalls,
282 // "> 1" means the processor is out-of-order. This is a machine independent
288 // LoopMicroOpBufferSize is the number of micro-ops that the processor may
290 // optimal number of micro-ops in a loop body. A loop may be partially
291 // unrolled to bring the count of micro-ops in the loop body closer to this
292 // number.
302 // By default, this is set to an arbitrarily high number of cycles
307 // MispredictPenalty is the typical number of extra cycles the processor
336 /// Does this machine model include instruction-level scheduling.
420 static const int NoInformationAvailable = -1;
451 if (!SCDesc || !SCDesc->isValid())