Lines Matching defs:OutMIs
58 NewMIVector OutMIs;
80 for (auto MIB : OutMIs) {
1045 if (NewInsnID >= OutMIs.size())
1046 OutMIs.resize(NewInsnID + 1);
1051 OutMIs[NewInsnID] = MachineInstrBuilder(*OldMI->getMF(), OldMI);
1052 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
1056 dbgs() << CurrentIdx << ": GIR_MutateOpcode(OutMIs["
1066 if (NewInsnID >= OutMIs.size())
1067 OutMIs.resize(NewInsnID + 1);
1069 OutMIs[NewInsnID] = Builder.buildInstr(Opcode);
1071 dbgs() << CurrentIdx << ": GIR_BuildMI(OutMIs["
1093 assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1094 OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx));
1097 << CurrentIdx << ": GIR_Copy(OutMIs[" << NewInsnID
1106 assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1108 MachineInstrBuilder &NewMI = OutMIs[NewInsnID];
1112 dbgs() << CurrentIdx << ": GIR_CopyRemaining(OutMIs["
1123 assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1126 OutMIs[NewInsnID].addReg(ZeroReg);
1128 OutMIs[NewInsnID].add(MO);
1130 dbgs() << CurrentIdx << ": GIR_CopyOrAddZeroReg(OutMIs["
1141 assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1142 OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
1145 dbgs() << CurrentIdx << ": GIR_CopySubReg(OutMIs["
1155 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1157 OutMIs[InsnID].addDef(RegNum, Flags);
1159 dbgs() << CurrentIdx << ": GIR_AddImplicitDef(OutMIs["
1167 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1168 OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
1170 dbgs() << CurrentIdx << ": GIR_AddImplicitUse(OutMIs["
1179 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1180 OutMIs[InsnID].addReg(RegNum, RegFlags);
1183 << CurrentIdx << ": GIR_AddRegister(OutMIs[" << InsnID
1190 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1191 OutMIs[InsnID].addIntrinsicID((Intrinsic::ID)Value);
1193 dbgs() << CurrentIdx << ": GIR_AddIntrinsicID(OutMIs["
1201 dbgs() << CurrentIdx << ": GIR_SetImplicitDefDead(OutMIs["
1203 MachineInstr *MI = OutMIs[InsnID];
1213 dbgs() << CurrentIdx << ": GIR_SetMIFlags(OutMIs["
1215 MachineInstr *MI = OutMIs[InsnID];
1224 dbgs() << CurrentIdx << ": GIR_UnsetMIFlags(OutMIs["
1226 MachineInstr *MI = OutMIs[InsnID];
1235 dbgs() << CurrentIdx << ": GIR_CopyMIFlags(OutMIs["
1237 MachineInstr *MI = OutMIs[InsnID];
1253 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1255 OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags,
1259 dbgs() << CurrentIdx << ": GIR_AddTempRegister(OutMIs[" << InsnID
1271 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1272 OutMIs[InsnID].addImm(Imm);
1274 dbgs() << CurrentIdx << ": GIR_AddImm(OutMIs[" << InsnID
1283 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1287 OutMIs[InsnID].addCImm(
1290 dbgs() << CurrentIdx << ": GIR_AddCImm(OutMIs[" << InsnID
1299 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1301 RenderOpFn(OutMIs[InsnID]);
1303 dbgs() << CurrentIdx << ": GIR_ComplexRenderer(OutMIs["
1311 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1312 State.Renderers[RendererID][RenderOpID](OutMIs[InsnID]);
1315 << ": GIR_ComplexSubOperandRenderer(OutMIs["
1325 MachineInstrBuilder &MI = OutMIs[InsnID];
1331 << ": GIR_ComplexSubOperandSubRegRenderer(OutMIs["
1340 assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1344 OutMIs[NewInsnID].addImm(
1347 OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(1));
1351 dbgs() << CurrentIdx << ": GIR_CopyConstantAsSImm(OutMIs["
1360 assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1364 OutMIs[NewInsnID].addFPImm(
1370 << CurrentIdx << ": GIR_CopyFPConstantAsFPImm(OutMIs["
1379 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1381 dbgs() << CurrentIdx << ": GIR_CustomRenderer(OutMIs["
1385 OutMIs[InsnID], *State.MIs[OldInsnID],
1395 if (runCustomAction(FnID, State, OutMIs)) {
1409 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1413 << ": GIR_CustomOperandRenderer(OutMIs[" << InsnID
1417 OutMIs[InsnID], *State.MIs[OldInsnID], OpIdx);
1424 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1425 MachineInstr &I = *OutMIs[InsnID].getInstr();
1432 dbgs() << CurrentIdx << ": GIR_ConstrainOperandRC(OutMIs["
1443 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1444 constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI,
1448 << ": GIR_ConstrainSelectedInstOperands(OutMIs["
1455 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1458 dbgs() << CurrentIdx << ": GIR_MergeMemOperands(OutMIs["
1465 OutMIs[InsnID].addMemOperand(MMO);