Lines Matching defs:NewInsnID

154       uint64_t NewInsnID = readULEB();
160       assert(NewInsnID != 0 && "Refusing to modify MIs[0]");
184       if ((size_t)NewInsnID < State.MIs.size())
185         State.MIs[NewInsnID] = NewMI;
187         assert((size_t)NewInsnID == State.MIs.size() &&
192                       dbgs() << CurrentIdx << ": MIs[" << NewInsnID
993       uint64_t NewInsnID = readULEB();
999                              << NewInsnID << "][" << NewOpIdx << "])\n");
1002       Register New = State.MIs[NewInsnID]->getOperand(NewOpIdx).getReg();
1043       uint64_t NewInsnID = readULEB();
1045       if (NewInsnID >= OutMIs.size())
1046         OutMIs.resize(NewInsnID + 1);
1051       OutMIs[NewInsnID] = MachineInstrBuilder(*OldMI->getMF(), OldMI);
1052       OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
1057                              << NewInsnID << "], MIs[" << OldInsnID << "], "
1064       uint64_t NewInsnID = (MatcherOpcode == GIR_BuildRootMI) ? 0 : readULEB();
1066       if (NewInsnID >= OutMIs.size())
1067         OutMIs.resize(NewInsnID + 1);
1069       OutMIs[NewInsnID] = Builder.buildInstr(Opcode);
1072                              << NewInsnID << "], " << Opcode << ")\n");
1088       uint64_t NewInsnID =
1093       assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1094       OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx));
1097                           << CurrentIdx << ": GIR_Copy(OutMIs[" << NewInsnID
1103       uint64_t NewInsnID = readULEB();
1106       assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1108       MachineInstrBuilder &NewMI = OutMIs[NewInsnID];
1113                              << NewInsnID << "], MIs[" << OldInsnID
1119       uint64_t NewInsnID = readULEB();
1123       assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1126         OutMIs[NewInsnID].addReg(ZeroReg);
1128         OutMIs[NewInsnID].add(MO);
1131                              << NewInsnID << "], MIs[" << OldInsnID << "], "
1137       uint64_t NewInsnID = readULEB();
1141       assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1142       OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
1146                              << NewInsnID << "], MIs[" << OldInsnID << "], "
1338       uint64_t NewInsnID = readULEB();
1340       assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1344         OutMIs[NewInsnID].addImm(
1347         OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(1));
1352                              << NewInsnID << "], MIs[" << OldInsnID << "])\n");
1358       uint64_t NewInsnID = readULEB();
1360       assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
1364         OutMIs[NewInsnID].addFPImm(
1371                           << NewInsnID << "], MIs[" << OldInsnID << "])\n");
1502       uint64_t NewInsnID = readULEB();
1508                              << NewInsnID << "][" << NewOpIdx << "])\n");
1511       Register New = State.MIs[NewInsnID]->getOperand(NewOpIdx).getReg();