Lines Matching defs:InsnID
155 uint64_t InsnID = readULEB();
162 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
193 << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx
213 uint64_t InsnID = readULEB();
219 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
220 unsigned Opcode = State.MIs[InsnID]->getOpcode();
223 dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID
237 uint64_t InsnID = readULEB();
242 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
243 const int64_t Opcode = State.MIs[InsnID]->getOpcode();
246 dbgs() << CurrentIdx << ": GIM_SwitchOpcode(MIs[" << InsnID << "], ["
267 uint64_t InsnID = readULEB();
273 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
274 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
277 dbgs() << CurrentIdx << ": GIM_SwitchType(MIs[" << InsnID
315 uint64_t InsnID = readULEB();
320 << (IsLE ? "LE" : "GE") << "(MIs[" << InsnID
322 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
323 const unsigned NumOps = State.MIs[InsnID]->getNumOperands();
331 uint64_t InsnID = readULEB();
335 << InsnID << "], Expected=" << Expected << ")\n");
336 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
337 if (State.MIs[InsnID]->getNumOperands() != Expected) {
345 uint64_t InsnID = readULEB();
351 << InsnID << "]->getOperand(" << OpIdx
353 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
354 assert((State.MIs[InsnID]->getOperand(OpIdx).isImm() ||
355 State.MIs[InsnID]->getOperand(OpIdx).isCImm()) &&
359 if (State.MIs[InsnID]->getOperand(OpIdx).isCImm())
360 Value = State.MIs[InsnID]->getOperand(OpIdx).getCImm()->getSExtValue();
361 else if (State.MIs[InsnID]->getOperand(OpIdx).isImm())
362 Value = State.MIs[InsnID]->getOperand(OpIdx).getImm();
372 uint64_t InsnID = readULEB();
377 << InsnID << "], Predicate=" << Predicate << ")\n");
378 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
379 assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
382 if (!State.MIs[InsnID]->getOperand(1).isCImm())
386 State.MIs[InsnID]->getOperand(1).getCImm()->getValue();
393 uint64_t InsnID = readULEB();
398 << InsnID << "], Predicate=" << Predicate << ")\n");
399 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
400 assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
402 assert(State.MIs[InsnID]->getOperand(1).isFPImm() &&
406 State.MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
415 uint64_t InsnID = readULEB();
420 << InsnID << "])\n");
421 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
423 const MachineInstr *MI = State.MIs[InsnID];
459 uint64_t InsnID = readULEB();
464 << InsnID << "], Predicate=" << Predicate << ")\n");
465 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
468 if (!testMIPredicate_MI(Predicate, *State.MIs[InsnID], State))
474 uint64_t InsnID = readULEB();
478 << InsnID << "]\n");
480 const MachineInstr *MI = State.MIs[InsnID];
492 uint64_t InsnID = readULEB();
496 << InsnID << "]\n");
498 const MachineInstr *MI = State.MIs[InsnID];
510 uint64_t InsnID = readULEB();
514 << InsnID << "], " << (uint64_t)Ordering << ")\n");
515 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
516 if (!State.MIs[InsnID]->hasOneMemOperand())
520 for (const auto &MMO : State.MIs[InsnID]->memoperands())
527 uint64_t InsnID = readULEB();
532 << InsnID << "], " << (uint64_t)Ordering << ")\n");
533 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
534 if (!State.MIs[InsnID]->hasOneMemOperand())
538 for (const auto &MMO : State.MIs[InsnID]->memoperands())
545 uint64_t InsnID = readULEB();
550 << InsnID << "], " << (uint64_t)Ordering << ")\n");
551 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
552 if (!State.MIs[InsnID]->hasOneMemOperand())
556 for (const auto &MMO : State.MIs[InsnID]->memoperands())
563 uint64_t InsnID = readULEB();
568 if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
579 *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
601 uint64_t InsnID = readULEB();
605 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
607 if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
614 *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
617 << "(MIs[" << InsnID << "]->memoperands() + "
626 uint64_t InsnID = readULEB();
632 << InsnID << "]->memoperands() + " << MMOIdx
634 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
636 if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
643 *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
657 uint64_t InsnID = readULEB();
668 << "LLT(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
670 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
672 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
681 if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
688 *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
708 uint64_t InsnID = (MatcherOpcode == GIM_RootCheckType) ? 0 : readULEB();
712 dbgs() << CurrentIdx << ": GIM_CheckType(MIs[" << InsnID
715 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
716 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
724 uint64_t InsnID = readULEB();
730 << InsnID << "]->getOperand(" << OpIdx
732 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
733 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
738 MachineFunction *MF = State.MIs[InsnID]->getParent()->getParent();
755 uint64_t InsnID = readULEB();
761 << InsnID << "]->getOperand(" << OpIdx
763 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
765 State.RecordedOperands[StoreIdx] = &State.MIs[InsnID]->getOperand(OpIdx);
769 uint64_t InsnID = readULEB();
775 << InsnID << "]->getOperand(" << OpIdx
777 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
781 const auto &Op = State.MIs[InsnID]->getOperand(OpIdx);
790 uint64_t InsnID =
796 << InsnID << "]->getOperand(" << OpIdx
798 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
799 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
811 uint64_t InsnID = readULEB();
817 << "] = GIM_CheckComplexPattern(MIs[" << InsnID
821 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
825 State.MIs[InsnID]->getOperand(OpIdx));
837 uint64_t InsnID = readULEB();
842 << InsnID << "]->getOperand(" << OpIdx
844 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
845 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
869 uint64_t InsnID = readULEB();
874 << InsnID << "]->getOperand(" << OpIdx
876 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
877 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
891 uint64_t InsnID = readULEB();
896 << InsnID << "]->getOperand(" << OpIdx
898 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
899 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
906 uint64_t InsnID = readULEB();
911 << InsnID << "]->getOperand(" << OpIdx
913 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
914 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
921 uint64_t InsnID = readULEB();
924 dbgs() << CurrentIdx << ": GIM_CheckIsMBB(MIs[" << InsnID
926 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
927 if (!State.MIs[InsnID]->getOperand(OpIdx).isMBB()) {
934 uint64_t InsnID = readULEB();
937 dbgs() << CurrentIdx << ": GIM_CheckIsImm(MIs[" << InsnID
939 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
940 if (!State.MIs[InsnID]->getOperand(OpIdx).isImm()) {
962 uint64_t InsnID = readULEB();
968 << InsnID << "][" << OpIdx << "], MIs["
970 assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
973 MachineOperand &Op = State.MIs[InsnID]->getOperand(OpIdx);
1010 uint64_t InsnID = readULEB();
1014 dbgs() << CurrentIdx << ": GIM_MIFlags(MIs[" << InsnID
1016 if ((State.MIs[InsnID]->getFlags() & Flags) != Flags) {
1023 uint64_t InsnID = readULEB();
1027 dbgs() << CurrentIdx << ": GIM_MIFlagsNot(MIs[" << InsnID
1029 if ((State.MIs[InsnID]->getFlags() & Flags)) {
1152 uint64_t InsnID = readULEB();
1155 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1157 OutMIs[InsnID].addDef(RegNum, Flags);
1160 << InsnID << "], " << RegNum << ")\n");
1165 uint64_t InsnID = readULEB();
1167 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1168 OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
1171 << InsnID << "], " << RegNum << ")\n");
1176 uint64_t InsnID = readULEB();
1179 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1180 OutMIs[InsnID].addReg(RegNum, RegFlags);
1183 << CurrentIdx << ": GIR_AddRegister(OutMIs[" << InsnID
1188 uint64_t InsnID = readULEB();
1190 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1191 OutMIs[InsnID].addIntrinsicID((Intrinsic::ID)Value);
1194 << InsnID << "], " << Value << ")\n");
1198 uint64_t InsnID = readULEB();
1202 << InsnID << "], OpIdx=" << OpIdx << ")\n");
1203 MachineInstr *MI = OutMIs[InsnID];
1209 uint64_t InsnID = readULEB();
1214 << InsnID << "], " << Flags << ")\n");
1215 MachineInstr *MI = OutMIs[InsnID];
1220 uint64_t InsnID = readULEB();
1225 << InsnID << "], " << Flags << ")\n");
1226 MachineInstr *MI = OutMIs[InsnID];
1231 uint64_t InsnID = readULEB();
1236 << InsnID << "], MIs[" << OldInsnID << "])\n");
1237 MachineInstr *MI = OutMIs[InsnID];
1244 uint64_t InsnID = readULEB();
1253 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1255 OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags,
1259 dbgs() << CurrentIdx << ": GIR_AddTempRegister(OutMIs[" << InsnID
1269 uint64_t InsnID = readULEB();
1271 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1272 OutMIs[InsnID].addImm(Imm);
1274 dbgs() << CurrentIdx << ": GIR_AddImm(OutMIs[" << InsnID
1280 uint64_t InsnID = readULEB();
1283 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1287 OutMIs[InsnID].addCImm(
1290 dbgs() << CurrentIdx << ": GIR_AddCImm(OutMIs[" << InsnID
1297 uint64_t InsnID = readULEB();
1299 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1301 RenderOpFn(OutMIs[InsnID]);
1304 << InsnID << "], " << RendererID << ")\n");
1308 uint64_t InsnID = readULEB();
1311 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1312 State.Renderers[RendererID][RenderOpID](OutMIs[InsnID]);
1316 << InsnID << "], " << RendererID << ", "
1321 uint64_t InsnID = readULEB();
1325 MachineInstrBuilder &MI = OutMIs[InsnID];
1332 << InsnID << "], " << RendererID << ", "
1376 uint64_t InsnID = readULEB();
1379 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1382 << InsnID << "], MIs[" << OldInsnID << "], "
1385 OutMIs[InsnID], *State.MIs[OldInsnID],
1405 uint64_t InsnID = readULEB();
1409 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1413 << ": GIR_CustomOperandRenderer(OutMIs[" << InsnID
1417 OutMIs[InsnID], *State.MIs[OldInsnID], OpIdx);
1421 uint64_t InsnID = readULEB();
1424 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1425 MachineInstr &I = *OutMIs[InsnID].getInstr();
1433 << InsnID << "], " << OpIdx << ", " << RCEnum
1440 uint64_t InsnID = (MatcherOpcode == GIR_RootConstrainSelectedInstOperands)
1443 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1444 constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI,
1449 << InsnID << "])\n");
1453 uint64_t InsnID = readULEB();
1455 assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
1459 << InsnID << "]");
1465 OutMIs[InsnID].addMemOperand(MMO);
1471 uint64_t InsnID = readULEB();
1472 MachineInstr *MI = State.MIs[InsnID];
1476 << InsnID << "])\n");