260 References  section in The Planning Process and VPlan Roadmap
262 .. [1] "Outer-loop vectorization: revisited for short SIMD architectures", Dorit
265 .. [2] "Proposal for function vectorization and loop vectorization with function
271 .. [3] "Throttling Automatic Vectorization: When Less is More", Vasileios
274 .. [4] "Exploiting mixed SIMD parallelism by reducing data reorganization
277 .. [5] "Register Allocation via Hierarchical Graph Coloring", David Callahan and
280 .. [6] "Structural analysis: A new approach to flow analysis in optimizing
283 .. [7] "Enabling Polyhedral Optimizations in LLVM", Tobias Grosser, Diploma
286 .. [8] "Introducing VPlan to the Loop Vectorizer", Gil Rapaport and Ayal Zaks,
289 .. [9] "Extending LoopVectorizer: OpenMP4.5 SIMD and Outer Loop
292 .. [10] "VPlan: Status Update and Future Roadmap", Ayal Zaks and Florian Hahn,