Lines Matching defs:LLVM

39 LLVM
846 The AMDGPU address spaces correspond to target architecture specific LLVM
847 address space numbers used in LLVM IR.
859      Address Space Name                    LLVM IR Address HSA Segment Hardware         Address NULL Value
985   *pointer*), allowing normal LLVM load/store/atomic operations to be used to
1002   be easily represented in LLVM (such as implicit swizzled access to structured
1042 This section provides LLVM memory synchronization scopes supported by the AMDGPU
1056   .. table:: AMDHSA LLVM Sync Scopes
1060      LLVM Sync Scope         Description
1134 LLVM IR Intrinsics
1137 The AMDGPU backend implements the following LLVM IR intrinsics.
1141 .. table:: AMDGPU LLVM IR Intrinsics
1145   LLVM Intrinsic                                   Description
1398                                                    Provides a way to convert i1 in LLVM IR to i32 or i64 lane mask - bitfield
1446 LLVM IR Metadata
1449 The AMDGPU backend implements the following target custom LLVM IR
1544 LLVM IR Attributes
1547 The AMDGPU backend supports the following LLVM IR attributes.
1549   .. table:: AMDGPU LLVM IR Attributes
1553      LLVM Attribute                          Description
1977     runtime ABI for code object V2. Can no longer be emitted by this version of LLVM.
1980     runtime ABI for code object V3. Can no longer be emitted by this version of LLVM.
2322   Code object V2 generation is no longer supported by this version of LLVM.
2340                                                  Finalizer and not the LLVM compiler.
2421   by the LLVM compiler. The LLVM compiler does not generate a
2441   feature is supported and enabled, the string produced by the LLVM compiler
2736 DWARF Version 4 and DWARF Version 5 as an LLVM vendor extension.
2921    Address Space Name                      Value Address Bit Size LLVM IR Address Space
2937 See :ref:`amdgpu-address-spaces` for information on the AMDGPU LLVM IR address
3134 The AMDGPU backend may generate the following pseudo LLVM MIR to manipulate the
3177 description of a vector of lane program locations, the LLVM MIR ``DBG_VALUE``
3204 The following provides an example using pseudo LLVM MIR.
3576 * The producer can generate either 32-bit or 64-bit DWARF format. LLVM generates
3630   Code object V2 generation is no longer supported by this version of LLVM.
4059   Code object V3 generation is no longer supported by this version of LLVM.
4513   of LLVM.
6151 This section describes the mapping of the LLVM memory model onto AMDGPU machine
6177     the LLVM ``memfence`` instruction does not allow an address space to be
6226      LLVM Memory  Optimization Constraints
6268 LLVM fences do not have address space information, thus, fence
6386      LLVM Instr   LLVM Memory  LLVM Memory    AMDGPU     AMDGPU Machine Code
7166                                                              since LLVM
7646      LLVM Instr   LLVM Memory  LLVM Memory    AMDGPU     AMDGPU Machine Code
9320                                                              since LLVM
9967      LLVM Instr   LLVM Memory  LLVM Memory    AMDGPU     AMDGPU Machine Code
11683                                                              since LLVM
12338      LLVM Instr   LLVM Memory  LLVM Memory    AMDGPU     AMDGPU Machine Code
13697                                                              since LLVM
14419 The mapping of LLVM IR syncscope to GFX12 instruction ``scope`` operands is
14430      LLVM syncscope      CU wavefront        WGP wavefront
14452      LLVM Instr   LLVM Memory  LLVM Memory    AMDGPU     AMDGPU Machine Code
17509 AMDGPU backend has LLVM-MC based assembler which is currently in development.
17808   Code object V2 generation is no longer supported by this version of LLVM.
17863   Code object V2 generation is no longer supported by this version of LLVM.
17938   Code object V2 generation is no longer supported by this version of LLVM.