Lines Matching defs:GFX11

472      **GCN GFX11 (RDNA 3)** [AMD-GCN-GFX11-RDNA3]_
502      **GCN GFX11 (RDNA 3.5)** [AMD-GCN-GFX11-RDNA3.5]_
897   GFX9-GFX11 the aperture base addresses are directly available as inline
967   GFX9-GFX11.
1581      "amdgpu-ieee" true/false.               GFX6-GFX11 Only
1585      "amdgpu-dx10-clamp" true/false.         GFX6-GFX11 Only
1679                                              target is available (GFX11+).
3531   For GFX9-GFX11 this is 4.
3534   For GFX9-GFX11 this is 1.
4016                                                            GFX6-GFX11. This
4032                                                            GFX6-GFX11
4828 supported except by flat and scratch instructions in GFX9-GFX11.
4831 GFX7-GFX11. This uses two fixed ranges of virtual addresses (the private and
4847 GFX9-GFX11 the aperture base addresses are directly available as inline constant
4972                                                      GFX10-GFX11
5035                                                      GFX10-GFX11
5239      21      1 bit   ENABLE_DX10_CLAMP               GFX9-GFX11
5268      23      1 bit   ENABLE_IEEE_MODE                GFX9-GFX11
5412      6       1 bit   ENABLE_TRAP_HANDLER             GFX6-GFX11
5514                                                      GFX7-GFX11
5572   .. table:: compute_pgm_rsrc3 for GFX10-GFX11
5584                                                      GFX11
5590                                                      GFX11
5600                                                      GFX11
5610                                                      GFX11
5789                                                   may be needed for GFX9-GFX11 which
5894 has V# 64-bit address support), flat instructions (GFX7-GFX11), or global
5895 instructions (GFX9-GFX11).
5972 GFX9-GFX11
6193 (GFX6-GFX8), or ``scratch_load/store`` (GFX9-GFX11). Since only a single thread
12200 Memory Model GFX10-GFX11
12203 For GFX10-GFX11:
12273 * On GFX10.3 and GFX11 a memory attached last level (MALL) cache exists for GPU memory.
12331 The code sequences used to implement the memory model for GFX10-GFX11 are defined in
12334   .. table:: AMDHSA Memory Model Code Sequences GFX10-GFX11
12339                   Ordering     Sync Scope     Address    GFX10-GFX11
12429                                                            - If GFX11, omit dlc=1.
12543                                                            - If GFX11, omit dlc=1.
12570                                                            - If GFX11, omit dlc=1.
16499      Usage               Code Sequence   GFX6-GFX8 Inputs GFX9-GFX11 Inputs Description
17510 It supports AMDGCN GFX6-GFX11.
17581     RDNA 3        :doc:`GFX11<AMDGPU/AMDGPUAsmGFX11>`           :doc:`gfx1100<AMDGPU/AMDGPUAsmGFX11>`
17596 [AMD-GCN-GFX11-RDNA3]_ and [AMD-GCN-GFX11-RDNA3.5]_.
17782 VOP3_DPP examples (Available on GFX11+):
18132                                                                                   GFX11-GFX12  :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx12-table`.
18181      ``.amdhsa_dx10_clamp``                                   1                   GFX6-GFX11   Controls ENABLE_DX10_CLAMP in
18183      ``.amdhsa_ieee_mode``                                    1                   GFX6-GFX11   Controls ENABLE_IEEE_MODE in
18191                                                               Specific            GFX11-GFX12
18201      ``.amdhsa_shared_vgpr_count``                            0                   GFX10-GFX11  Controls SHARED_VGPR_COUNT in
18393 .. [AMD-GCN-GFX11-RDNA3] `AMD RDNA 3 Instruction Set Architecture <https://developer.amd.com/wp-content/resources/RDNA3_Shader_ISA_December2022.pdf>`__
18394 .. [AMD-GCN-GFX11-RDNA3.5] `AMD RDNA 3.5 Instruction Set Architecture <https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna35_instruction_set_architecture.pdf>`__