Lines Matching +full:- +full:d
7 beautification by scripts. The fields are: name (N), email (E), web-address
8 (W), PGP key ID and fingerprint (P), description (D), snail-mail address
14 D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
18 D: LCSSA pass and related LoopUnswitch work
19 D: GVNPRE pass, DataLayout refactoring, random improvements
22 D: MingW Win32 API portability layer
26 D: Clang frontend, frontend attributes, Windows support, general bug fixing
31 D: Clang frontend, OpenMP in clang, SLP vectorizer, Loop vectorizer, InstCombine
36 D: PowerPC backend developer
37 D: Target-independent code generator and analysis improvements
41 D: ET-Forest implementation.
42 D: Sparse bitmap
47 D: AArch64 backend improvements
48 D: Added EarlyCSE MemorySSA support
49 D: CodeGen improvements
53 D: General bug fixing/fit & finish, mostly in Clang
57 D: APFloat implementation.
61 D: RISC-V backend
66 D: Portions of X86 and Sparc JIT compilers, PowerPC backend
67 D: Incremental bitcode loader
71 D: The `mem2reg' pass - promotes values stored in memory to registers
75 D: Loop unrolling with run-time trip counts.
80 D: Hashing algorithms and interfaces
81 D: Inline cost analysis
82 D: Machine block placement pass
83 D: SROA
87 D: Fixes to the Reassociation pass, various improvement patches
91 D: ARM and X86 backends
92 D: Instruction scheduler improvements
93 D: Register allocator improvements
94 D: Loop optimizer improvements
95 D: Target-independent code generator improvements
101 D: LLVM Makefile improvements
102 D: Clang diagnostic & driver tweaks
106 E: jeffc@jolt-lang.org
107 W: http://jolt-lang.org
108 D: Native Win32 API portability layer
112 D: Original Autoconf support, documentation improvements, bug fixes
116 D: Deterministic finite automaton based infrastructure for VLIW packetization
120 D: Bug fixes and minor improvements
124 D: MC and LLD work
128 D: AArch64 machine description for Cortex-A53
132 D: Linear scan register allocator, many codegen improvements, Java frontend
136 D: Basic-block autovectorization, PowerPC backend improvements
140 D: LIT patches and documentation
144 D: Miscellaneous bug fixes
149 D: Portions of X86 static and JIT compilers; initial SparcV8 backend
150 D: Dynamic trace optimizer
151 D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
155 W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
156 D: PPC backend fixes for Linux
160 D: Portions of the PowerPC backend
164 D: Callgraph class cleanups
168 D: Author of llvmc2
172 D: Miscellaneous bug fixes
173 D: WebAssembly Backend
178 D: ARM/AArch64 back-end improvements
179 D: Loop Vectorizer improvements
180 D: Regression and Test Suite improvements
181 D: Linux compatibility (GNU, musl, etc)
182 D: Initial Linux kernel / Android support effort
187 D: Thumb-2 code generator
191 D: Miscellaneous bug fixes
192 D: Register allocation refactoring
196 D: Improvements for space efficiency
201 D: SjLj exception handling support
202 D: General fixes and improvements for the ARM back-end
203 D: MCJIT
204 D: ARM integrated assembler and assembly parser
205 D: Led effort for the backend formerly known as ARM64
209 D: PBQP-based register allocator
213 D: Pluggable GC support
214 D: C interface
215 D: Ocaml bindings
219 D: JIT support for ARM
223 D: Visual C++ compatibility fixes
227 D: Nightly Tester
231 D: PowerPC Backend Developer
232 D: Improvements to the PPC backend and miscellaneous bug fixes
236 D: ARM constant islands improvements
237 D: Tail merging improvements
238 D: Rewrite X87 back end
239 D: Use APFloat for floating point constants widely throughout compiler
240 D: Implement X87 long double
244 D: Support for packed types
248 D: Author of LLVM Ada bindings
252 D: A variety of Clang contributions including function multiversioning, regcall/vectorcall.
257 D: llvm-config script
261 D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
262 D: x86/linux PIC codegen, aliases, regparm/visibility attributes
263 D: Switch lowering refactoring
267 D: Author of the original C backend
271 D: Miscellaneous bug fixes
275 D: Loop Vectorizer
279 D: Implemented DFA-based target independent VLIW packetizer
283 D: aligned load/store support, parts of noalias and restrict support
284 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
285 D: address spaces
289 D: Improvements to the PPC backend, instruction scheduling
290 D: Debug and Dwarf implementation
291 D: Auto upgrade mangler
292 D: llvm-gcc4 svn wrangler
297 D: Primary architect of LLVM
302 D: The initial llvm-ar tool, converted regression testsuite to dejagnu
303 D: Modulo scheduling in the SparcV9 backend
304 D: Release manager (1.7+)
310 D: Debian and Ubuntu packaging
311 D: Continuous integration with jenkins
316 D: Alpha backend
317 D: Sampling based profiling
321 D: PredicateSimplifier pass
325 D: Backend for Qualcomm's Hexagon VLIW processor.
331 D: Mips backend
332 D: Random ARM integrated assembler and assembly parser improvements
333 D: General X86 AVX1 support
337 D: LoongArch backend
341 W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
342 D: IA64 backend, BigBlock register allocator
346 D: Clang semantic analysis and IR generation
350 D: Line number support for llvmgcc
354 D: z/OS support
358 D: Test suite fixes for FreeBSD
362 D: Added STI Cell SPU backend.
366 D: Support for implicit TLS model used with MS VC runtime
367 D: Dumping of Win64 EH structures
373 D: Maintaining the Git monorepo
374 W: https://github.com/llvm-project/
380 D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
381 D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
382 D: and error clean ups.
386 D: Visual C++ compatibility fixes
390 D: Machine code verifier
391 D: Blackfin backend
392 D: Fast register allocator
393 D: Greedy register allocator
397 D: XCore backend
401 D: !invariant.group metadata and other intrinsics for devirtualization in clang
405 D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
406 D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
407 D: Optimizer improvements, Loop Index Split
411 D: Fixes and improvements to the AArch64 backend
416 D: MicroBlaze backend
420 D: MSVC support
423 E: llvm-dev@redking.me.uk
424 D: X86 backend, Selection DAG, Scheduler Models and Cost Tables.
428 D: Debug Information
433 D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
437 D: Some bugfixes to CellSPU
441 D: Cmake dependency chain and various bug fixes
446 D: ARM calling conventions rewrite, hard float support
451 D: AArch64 fast instruction selection pass
452 D: Fixes and improvements to the ARM fast-isel pass
453 D: Fixes and improvements to the AArch64 backend
457 D: X86 code generation improvements, Loop Vectorizer, SLP Vectorizer
461 D: MSIL backend
466 D: Ada support in llvm-gcc
467 D: Dragonegg plugin
468 D: Exception handling improvements
469 D: Type legalizer rewrite
473 D: Graph coloring register allocator for the Sparc64 backend
477 D: MemorySSA, BatchAA, misc loop and new pass manager work.
481 D: Tail call optimization for the x86 backend
485 D: Miscellaneous bug fixes
489 D: The `paths' pass
493 D: Shepherding Windows COFF support into MC.
494 D: Lots of Windows stuff.
499 D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
503 D: z/OS support
508 D: C++ frontend next generation standards implementation
512 D: X86 codegen and disassembler improvements. AVX2 support.
516 D: Miscellaneous bug fixes
520 D: C++ bugs filed, and C++ front-end bug fixes.
524 D: Instruction Scheduling, ...
528 D: ARM backend improvements
529 D: Thread Local Storage implementation
533 D: X86 bug fixes and new instruction support.
538 D: Release manager, IR Linker, LTO.
539 D: Bunches of stuff.
543 D: Advanced SIMD (NEON) support in the ARM backend.
551 D: PowerPC Backend Developer
559 D: PowerPC Backend Developer
563 D: PowerPC Backend Developer
566 E: djordje.todorovic@rt-rk.com
567 D: Debug Information
571 D: PowerPC Analysis