Lines Matching defs:ArchSpec
1 //===-- ArchSpec.cpp ------------------------------------------------------===//
9 #include "lldb/Utility/ArchSpec.h"
26 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
37 ArchSpec::Core core;
43 // This core information can be looked using the ArchSpec::Core as the index
45 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
47 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
49 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
51 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
53 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
55 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
57 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
59 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
61 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
63 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7a,
65 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
67 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
69 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
71 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
73 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
75 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
77 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
79 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
81 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
83 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
85 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
87 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
89 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
91 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
93 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
95 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
97 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
99 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
101 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
104 ArchSpec::eCore_arm_arm64, "arm64"},
106 ArchSpec::eCore_arm_armv8, "armv8"},
108 ArchSpec::eCore_arm_armv8a, "armv8a"},
109 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l,
112 ArchSpec::eCore_arm_arm64e, "arm64e"},
114 ArchSpec::eCore_arm_arm64_32, "arm64_32"},
116 ArchSpec::eCore_arm_aarch64, "aarch64"},
119 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
121 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
123 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
125 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
127 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
129 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
132 ArchSpec::eCore_mips32r2el, "mipsr2el"},
134 ArchSpec::eCore_mips32r3el, "mipsr3el"},
136 ArchSpec::eCore_mips32r5el, "mipsr5el"},
138 ArchSpec::eCore_mips32r6el, "mipsr6el"},
141 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
143 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
145 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
147 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
149 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
152 ArchSpec::eCore_mips64el, "mips64el"},
154 ArchSpec::eCore_mips64r2el, "mips64r2el"},
156 ArchSpec::eCore_mips64r3el, "mips64r3el"},
158 ArchSpec::eCore_mips64r5el, "mips64r5el"},
160 ArchSpec::eCore_mips64r6el, "mips64r6el"},
163 {eByteOrderLittle, 2, 2, 4, llvm::Triple::msp430, ArchSpec::eCore_msp430,
166 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
168 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
170 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
172 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
174 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
176 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
178 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
180 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
182 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
184 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
186 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
188 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
190 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
194 ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
195 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
198 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
201 ArchSpec::eCore_s390x_generic, "s390x"},
204 ArchSpec::eCore_sparc_generic, "sparc"},
206 ArchSpec::eCore_sparc9_generic, "sparcv9"},
208 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
210 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
213 ArchSpec::eCore_x86_32_i486sx, "i486sx"},
214 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
218 ArchSpec::eCore_x86_64_x86_64, "x86_64"},
220 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"},
222 ArchSpec::eCore_x86_64_amd64, "amd64"},
225 ArchSpec::eCore_hexagon_generic, "hexagon"},
227 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"},
229 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
231 {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
233 {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
237 ArchSpec::eCore_loongarch32, "loongarch32"},
239 ArchSpec::eCore_loongarch64, "loongarch64"},
242 ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
244 ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
245 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
247 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"},
249 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32,
255 // ArchSpec::Core enumeration.
257 ArchSpec::kNumCores,
261 ArchSpec::Core core;
275 void ArchSpec::ListSupportedArchNames(StringList &list) {
280 void ArchSpec::AutoComplete(CompletionRequest &request) {
296 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX},
297 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
298 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
299 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
300 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
301 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
302 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
303 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
304 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
305 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK},
306 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
307 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
308 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
309 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
310 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
311 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
312 {ArchSpec::eCore_arm_arm64e, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK},
313 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK},
314 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK},
315 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK},
316 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK},
317 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK},
318 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
319 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
320 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
321 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
322 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
323 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
324 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
325 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
326 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
327 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
328 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
329 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
330 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
331 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX},
332 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
333 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK},
334 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK},
335 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK},
336 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK},
337 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK},
338 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK},
339 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK},
340 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK},
341 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK},
342 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK},
343 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK},
344 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK},
345 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
346 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
347 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK},
348 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK},
349 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK},
350 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK},
351 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX},
352 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK},
353 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK},
354 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK},
355 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX},
357 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
358 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}};
371 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
373 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
375 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
377 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
379 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64,
380 ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
381 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64,
382 ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
383 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
385 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
387 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
389 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
391 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
393 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32,
395 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
396 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
397 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
398 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
399 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
400 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
401 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
402 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
403 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
404 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
405 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64,
407 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
408 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
409 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
410 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
411 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
412 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
413 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
414 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
415 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
416 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
417 {ArchSpec::eCore_msp430, llvm::ELF::EM_MSP430, LLDB_INVALID_CPUTYPE,
419 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
421 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
423 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu,
425 {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
426 ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
427 {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
428 ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
429 {ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH,
430 ArchSpec::eLoongArchSubType_loongarch32, 0xFFFFFFFFu,
432 {ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH,
433 ArchSpec::eLoongArchSubType_loongarch64, 0xFFFFFFFFu,
445 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
447 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
449 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
451 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
453 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
455 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
457 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
459 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
471 {ArchSpec::eCore_ppc_generic, llvm::XCOFF::TCPU_COM, LLDB_INVALID_CPUTYPE,
473 {ArchSpec::eCore_ppc64_generic, llvm::XCOFF::TCPU_PPC64,
509 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) {
531 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) {
546 ArchSpec::ArchSpec() = default;
548 ArchSpec::ArchSpec(const char *triple_cstr) {
553 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
555 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
557 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
561 ArchSpec::~ArchSpec() = default;
563 void ArchSpec::Clear() {
573 const char *ArchSpec::GetArchitectureName() const {
580 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
582 std::string ArchSpec::GetTargetABI() const {
587 switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
588 case ArchSpec::eMIPSABI_N64:
591 case ArchSpec::eMIPSABI_N32:
594 case ArchSpec::eMIPSABI_O32:
604 void ArchSpec::SetFlags(const std::string &elf_abi) {
609 flag |= ArchSpec::eMIPSABI_N64;
611 flag |= ArchSpec::eMIPSABI_N32;
613 flag |= ArchSpec::eMIPSABI_O32;
618 std::string ArchSpec::GetClangTargetCPU() const {
622 case ArchSpec::eCore_mips32:
623 case ArchSpec::eCore_mips32el:
626 case ArchSpec::eCore_mips32r2:
627 case ArchSpec::eCore_mips32r2el:
630 case ArchSpec::eCore_mips32r3:
631 case ArchSpec::eCore_mips32r3el:
634 case ArchSpec::eCore_mips32r5:
635 case ArchSpec::eCore_mips32r5el:
638 case ArchSpec::eCore_mips32r6:
639 case ArchSpec::eCore_mips32r6el:
642 case ArchSpec::eCore_mips64:
643 case ArchSpec::eCore_mips64el:
646 case ArchSpec::eCore_mips64r2:
647 case ArchSpec::eCore_mips64r2el:
650 case ArchSpec::eCore_mips64r3:
651 case ArchSpec::eCore_mips64r3el:
654 case ArchSpec::eCore_mips64r5:
655 case ArchSpec::eCore_mips64r5el:
658 case ArchSpec::eCore_mips64r6:
659 case ArchSpec::eCore_mips64r6el:
672 uint32_t ArchSpec::GetMachOCPUType() const {
684 uint32_t ArchSpec::GetMachOCPUSubType() const {
696 uint32_t ArchSpec::GetDataByteSize() const {
700 uint32_t ArchSpec::GetCodeByteSize() const {
704 llvm::Triple::ArchType ArchSpec::GetMachine() const {
712 uint32_t ArchSpec::GetAddressByteSize() const {
726 ByteOrder ArchSpec::GetDefaultEndian() const {
733 bool ArchSpec::CharIsSignedByDefault() const {
759 lldb::ByteOrder ArchSpec::GetByteOrder() const {
768 bool ArchSpec::SetTriple(const llvm::Triple &triple) {
775 ArchSpec &arch) {
810 bool ArchSpec::SetTriple(llvm::StringRef triple) {
823 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
830 void ArchSpec::MergeFrom(const ArchSpec &other) {
857 // If this and other are both arm ArchSpecs and this ArchSpec is a generic
858 // "some kind of arm" spec but the other ArchSpec is a specific arm core,
862 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
863 other.GetCore() != ArchSpec::eCore_arm_generic) {
872 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
898 // the ArchSpec::TripleVendorWasSpecified() method says that any
951 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const {
958 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const {
996 bool ArchSpec::IsMatch(const ArchSpec &rhs, MatchType match) const {
1073 void ArchSpec::UpdateCore() {
1090 void ArchSpec::CoreUpdated(bool update_triple) {
1106 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1112 case ArchSpec::kCore_any:
1115 case ArchSpec::eCore_arm_generic:
1119 case ArchSpec::kCore_arm_any:
1120 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1122 if (core2 >= ArchSpec::kCore_thumb_first &&
1123 core2 <= ArchSpec::kCore_thumb_last)
1125 if (core2 == ArchSpec::kCore_arm_any)
1129 case ArchSpec::kCore_x86_32_any:
1130 if ((core2 >= ArchSpec::kCore_x86_32_first &&
1131 core2 <= ArchSpec::kCore_x86_32_last) ||
1132 (core2 == ArchSpec::kCore_x86_32_any))
1136 case ArchSpec::kCore_x86_64_any:
1137 if ((core2 >= ArchSpec::kCore_x86_64_first &&
1138 core2 <= ArchSpec::kCore_x86_64_last) ||
1139 (core2 == ArchSpec::kCore_x86_64_any))
1143 case ArchSpec::kCore_ppc_any:
1144 if ((core2 >= ArchSpec::kCore_ppc_first &&
1145 core2 <= ArchSpec::kCore_ppc_last) ||
1146 (core2 == ArchSpec::kCore_ppc_any))
1150 case ArchSpec::kCore_ppc64_any:
1151 if ((core2 >= ArchSpec::kCore_ppc64_first &&
1152 core2 <= ArchSpec::kCore_ppc64_last) ||
1153 (core2 == ArchSpec::kCore_ppc64_any))
1157 case ArchSpec::kCore_hexagon_any:
1158 if ((core2 >= ArchSpec::kCore_hexagon_first &&
1159 core2 <= ArchSpec::kCore_hexagon_last) ||
1160 (core2 == ArchSpec::kCore_hexagon_any))
1168 case ArchSpec::eCore_arm_armv7em:
1170 if (core2 == ArchSpec::eCore_arm_generic)
1172 if (core2 == ArchSpec::eCore_arm_armv7m)
1174 if (core2 == ArchSpec::eCore_arm_armv6m)
1176 if (core2 == ArchSpec::eCore_arm_armv7)
1186 case ArchSpec::eCore_arm_armv7m:
1188 if (core2 == ArchSpec::eCore_arm_generic)
1190 if (core2 == ArchSpec::eCore_arm_armv6m)
1192 if (core2 == ArchSpec::eCore_arm_armv7)
1194 if (core2 == ArchSpec::eCore_arm_armv7em)
1204 case ArchSpec::eCore_arm_armv6m:
1206 if (core2 == ArchSpec::eCore_arm_generic)
1208 if (core2 == ArchSpec::eCore_arm_armv7em)
1210 if (core2 == ArchSpec::eCore_arm_armv7)
1212 if (core2 == ArchSpec::eCore_arm_armv6m)
1218 case ArchSpec::eCore_arm_armv7f:
1219 case ArchSpec::eCore_arm_armv7k:
1220 case ArchSpec::eCore_arm_armv7s:
1221 case ArchSpec::eCore_arm_armv7l:
1222 case ArchSpec::eCore_arm_armv8l:
1224 if (core2 == ArchSpec::eCore_arm_generic)
1226 if (core2 == ArchSpec::eCore_arm_armv7)
1232 case ArchSpec::eCore_x86_64_x86_64h:
1233 case ArchSpec::eCore_x86_64_amd64:
1236 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1241 case ArchSpec::eCore_arm_armv8:
1243 if (core2 == ArchSpec::eCore_arm_arm64)
1245 if (core2 == ArchSpec::eCore_arm_aarch64)
1247 if (core2 == ArchSpec::eCore_arm_arm64e)
1253 case ArchSpec::eCore_arm_arm64e:
1255 if (core2 == ArchSpec::eCore_arm_arm64)
1257 if (core2 == ArchSpec::eCore_arm_aarch64)
1259 if (core2 == ArchSpec::eCore_arm_armv8)
1264 case ArchSpec::eCore_arm_aarch64:
1266 if (core2 == ArchSpec::eCore_arm_arm64)
1268 if (core2 == ArchSpec::eCore_arm_armv8)
1270 if (core2 == ArchSpec::eCore_arm_arm64e)
1276 case ArchSpec::eCore_arm_arm64:
1278 if (core2 == ArchSpec::eCore_arm_aarch64)
1280 if (core2 == ArchSpec::eCore_arm_armv8)
1282 if (core2 == ArchSpec::eCore_arm_arm64e)
1288 case ArchSpec::eCore_arm_arm64_32:
1290 if (core2 == ArchSpec::eCore_arm_generic)
1296 case ArchSpec::eCore_mips32:
1298 if (core2 >= ArchSpec::kCore_mips32_first &&
1299 core2 <= ArchSpec::kCore_mips32_last)
1305 case ArchSpec::eCore_mips32el:
1307 if (core2 >= ArchSpec::kCore_mips32el_first &&
1308 core2 <= ArchSpec::kCore_mips32el_last)
1314 case ArchSpec::eCore_mips64:
1316 if (core2 >= ArchSpec::kCore_mips32_first &&
1317 core2 <= ArchSpec::kCore_mips32_last)
1319 if (core2 >= ArchSpec::kCore_mips64_first &&
1320 core2 <= ArchSpec::kCore_mips64_last)
1326 case ArchSpec::eCore_mips64el:
1328 if (core2 >= ArchSpec::kCore_mips32el_first &&
1329 core2 <= ArchSpec::kCore_mips32el_last)
1331 if (core2 >= ArchSpec::kCore_mips64el_first &&
1332 core2 <= ArchSpec::kCore_mips64el_last)
1338 case ArchSpec::eCore_mips64r2:
1339 case ArchSpec::eCore_mips64r3:
1340 case ArchSpec::eCore_mips64r5:
1342 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1344 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1350 case ArchSpec::eCore_mips64r2el:
1351 case ArchSpec::eCore_mips64r3el:
1352 case ArchSpec::eCore_mips64r5el:
1354 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1356 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1362 case ArchSpec::eCore_mips32r2:
1363 case ArchSpec::eCore_mips32r3:
1364 case ArchSpec::eCore_mips32r5:
1366 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1371 case ArchSpec::eCore_mips32r2el:
1372 case ArchSpec::eCore_mips32r3el:
1373 case ArchSpec::eCore_mips32r5el:
1375 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1380 case ArchSpec::eCore_mips32r6:
1382 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1387 case ArchSpec::eCore_mips32r6el:
1389 if (core2 == ArchSpec::eCore_mips32el ||
1390 core2 == ArchSpec::eCore_mips32r6el)
1395 case ArchSpec::eCore_mips64r6:
1397 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1399 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1404 case ArchSpec::eCore_mips64r6el:
1406 if (core2 == ArchSpec::eCore_mips32el ||
1407 core2 == ArchSpec::eCore_mips32r6el)
1409 if (core2 == ArchSpec::eCore_mips64el ||
1410 core2 == ArchSpec::eCore_mips64r6el)
1423 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1424 const ArchSpec::Core lhs_core = lhs.GetCore();
1425 const ArchSpec::Core rhs_core = rhs.GetCore();
1430 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1434 bool ArchSpec::IsFullySpecifiedTriple() const {
1449 bool ArchSpec::IsAlwaysThumbInstructions() const {
1461 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m ||
1462 GetCore() == ArchSpec::Core::eCore_arm_armv7em ||
1463 GetCore() == ArchSpec::Core::eCore_arm_armv6m ||
1464 GetCore() == ArchSpec::Core::eCore_thumbv7m ||
1465 GetCore() == ArchSpec::Core::eCore_thumbv7em ||
1466 GetCore() == ArchSpec::Core::eCore_thumbv6m) {
1476 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {