Lines Matching defs:SVE

43   0x40b /* ARM Scalable Matrix Extension, Streaming SVE mode */
99     // Read SVE header to check for SVE support.
114       // streaming SVE mode.
291       // SVE is disabled take legacy route for FPU register access
300       // SVE or SSVE enabled, we will read and cache SVE ptrace data.
301       // In SIMD or Full mode, the data comes from the SVE regset. In streaming
302       // mode it comes from the streaming SVE regset.
325         // Extract SVE Z register value register number for this reg_info
345       return Status::FromErrorString("SVE disabled or not supported");
351       // SVE enabled, we will read and cache SVE ptrace data
357         // In FPSIMD state SVE payload mirrors legacy fpsimd struct and so
359         // other SVE register will be set to zero.
495       // SVE is disabled take legacy route for FPU register access
507       // SVE enabled, we will read and cache SVE ptrace data.
530         // Extract SVE Z register value register number for this reg_info
544       return Status::FromErrorString("SVE disabled or not supported");
546       // Target has SVE enabled, we will read and cache SVE ptrace data
572         return Status::FromErrorString("SVE vector length update failed.");
575       // If target supports SVE but currently in FPSIMD mode.
577         // Here we will check if writing this SVE register enables
600           // first 16 bytes only as SVE payload mirrors legacy fpsimd structure
609               "SVE state change operation not supported");
696   SVE, // Used for SVE and SSVE.
697   FPR, // When there is no SVE, or SVE in FPSIMD mode.
765   // If SVE is enabled we need not copy FPR separately.
808   // AArch64 register data must contain GPRs and either FPR or SVE registers.
809   // SVE registers can be non-streaming (aka SVE) or streaming (aka SSVE).
829   // Streaming SVE and the ZA register both use the streaming vector length.
845   // * Write SVE registers, which also clears SVCR.SM but most importantly, puts
846   //   us into full SVE mode instead of FPSIMD mode (where the registers are
851   // Restoring in different orders leads to things like the SVE registers being
869     dst = AddRegisterSetType(dst, RegisterSetType::SVE);
928   // AArch64 register data must contain GPRs, either FPR or SVE registers
935   // on size of remaining register data either SVE or FPRs should be restored
936   // next. SVE is not enabled if we have register data size less than or equal
979     case RegisterSetType::SVE:
984       // First write SVE header. We do not use RestoreRegisters because we do
991             "Invalid SVE header in data_sp",
1000       // SVE header has been written configure SVE vector length if needed.
1289   // Update SVE and ZA registers in case there is change in configuration.
1637   // on every stop and configures SVE vector length and whether we are in
1638   // streaming SVE mode.
1642     // If we have SVE we may also have the SVE streaming mode that SME added.
1646     // Check whether SME is present and the streaming SVE mode is active.
1652     // Streaming mode is active if the header has the SVE active flag set.
1661         // If SVE is enabled thread can switch between SVEState::FPSIMD and
1674       // On every stop we configure SVE vector length by calling
1736   // SVE, non-streaming vector length.