Lines Matching defs:emulator
111 bool Rd::Write(EmulateInstructionRISCV &emulator, uint64_t value) {
118 return emulator.WriteRegister(ctx, eRegisterKindLLDB, lldb_reg,
122 bool Rd::WriteAPFloat(EmulateInstructionRISCV &emulator, APFloat value) {
129 return emulator.WriteRegister(ctx, eRegisterKindLLDB, lldb_reg,
133 std::optional<uint64_t> Rs::Read(EmulateInstructionRISCV &emulator) {
136 return emulator.ReadRegister(eRegisterKindLLDB, lldbReg, value)
141 std::optional<int32_t> Rs::ReadI32(EmulateInstructionRISCV &emulator) {
143 Read(emulator), [](uint64_t value) { return int32_t(uint32_t(value)); });
146 std::optional<int64_t> Rs::ReadI64(EmulateInstructionRISCV &emulator) {
147 return transformOptional(Read(emulator),
151 std::optional<uint32_t> Rs::ReadU32(EmulateInstructionRISCV &emulator) {
152 return transformOptional(Read(emulator),
156 std::optional<APFloat> Rs::ReadAPFloat(EmulateInstructionRISCV &emulator,
160 if (!emulator.ReadRegister(eRegisterKindLLDB, lldbReg, value))
220 LoadStoreAddr(EmulateInstructionRISCV &emulator, I inst) {
221 return transformOptional(inst.rs1.Read(emulator), [&](uint64_t rs1) {
229 Load(EmulateInstructionRISCV &emulator, I inst, uint64_t (*extend)(E)) {
230 auto addr = LoadStoreAddr(emulator, inst);
234 emulator.ReadMem<T>(*addr),
235 [&](T t) { return inst.rd.Write(emulator, extend(E(t))); })
241 Store(EmulateInstructionRISCV &emulator, I inst) {
242 auto addr = LoadStoreAddr(emulator, inst);
246 inst.rs2.Read(emulator),
247 [&](uint64_t rs2) { return emulator.WriteMem<T>(*addr, rs2); })
255 AtomicAddr(EmulateInstructionRISCV &emulator, I inst, unsigned int align) {
256 return transformOptional(inst.rs1.Read(emulator),
267 AtomicSwap(EmulateInstructionRISCV &emulator, I inst, int align,
269 auto addr = AtomicAddr(emulator, inst, align);
273 zipOpt(emulator.ReadMem<T>(*addr), inst.rs2.Read(emulator)),
276 return emulator.WriteMem<T>(*addr, T(rs2)) &&
277 inst.rd.Write(emulator, extend(tmp));
284 AtomicADD(EmulateInstructionRISCV &emulator, I inst, int align,
286 auto addr = AtomicAddr(emulator, inst, align);
290 zipOpt(emulator.ReadMem<T>(*addr), inst.rs2.Read(emulator)),
293 return emulator.WriteMem<T>(*addr, T(tmp + rs2)) &&
294 inst.rd.Write(emulator, extend(tmp));
301 AtomicBitOperate(EmulateInstructionRISCV &emulator, I inst, int align,
303 auto addr = AtomicAddr(emulator, inst, align);
307 zipOpt(emulator.ReadMem<T>(*addr), inst.rs2.Read(emulator)),
310 return emulator.WriteMem<T>(*addr, operate(value, T(rs2))) &&
311 inst.rd.Write(emulator, extend(value));
318 AtomicCmp(EmulateInstructionRISCV &emulator, I inst, int align,
320 auto addr = AtomicAddr(emulator, inst, align);
324 zipOpt(emulator.ReadMem<T>(*addr), inst.rs2.Read(emulator)),
327 return emulator.WriteMem<T>(*addr, cmp(value, T(rs2))) &&
328 inst.rd.Write(emulator, extend(value));
333 bool AtomicSequence(EmulateInstructionRISCV &emulator) {
341 const auto pc = emulator.ReadPC();
348 auto inst = emulator.ReadInstructionAt(current_pc);
354 inst = emulator.ReadInstructionAt(current_pc += 4);
364 inst = emulator.ReadInstructionAt(current_pc += 4);
370 inst = emulator.ReadInstructionAt(current_pc += 4);
381 return exit_pc == current_pc && emulator.WritePC(current_pc);
678 Executor(EmulateInstructionRISCV &emulator, bool ignoreCond, bool is_rvc)
679 : m_emu(emulator), m_ignore_cond(ignoreCond), m_is_rvc(is_rvc) {}