Lines Matching defs:ARM

1 //===- ARM.cpp ------------------------------------------------------------===//
29 class ARM final : public TargetInfo {
31   ARM(Ctx &);
61 ARM::ARM(Ctx &ctx) : TargetInfo(ctx) {
79 uint32_t ARM::calcEFlags() const {
103 RelExpr ARM::getRelExpr(RelType type, const Symbol &s,
204 RelType ARM::getDynRel(RelType type) const {
210 void ARM::writeGotPlt(uint8_t *buf, const Symbol &) const {
214 void ARM::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
215   // An ARM entry is the address of the ifunc resolver function.
236 // only used if the target does not have the ARM ISA.
243 void ARM::writePltHeader(uint8_t *buf) const {
301 void ARM::addPltHeaderSymbols(InputSection &isec) const {
325 void ARM::writePlt(uint8_t *buf, const Symbol &sym,
378 void ARM::addPltSymbols(InputSection &isec, uint64_t off) const {
387 bool ARM::needsThunk(RelExpr expr, RelType type, const InputFile *file,
396   // A state change from ARM to Thumb and vice versa must go through an
403     // Source is ARM, all PLT entries are ARM so no interworking required.
406            "If the source is ARM, we should not need Thumb PLTs");
417     // Source is Thumb, when all PLT entries are ARM interworking is required.
418     // Otherwise we need to interwork if STT_FUNC Symbol has bit 0 clear (ARM).
432 uint32_t ARM::getThunkSectionSpacing() const {
446   // ARM B, BL, BLX range +/- 32MiB
466 bool ARM::inBranchRange(RelType type, uint64_t src, uint64_t dst) const {
468     // Destination is ARM, if ARM caller then Src is already 4-byte aligned.
495 // a non STT_FUNC symbol that may result in incorrect interworking between ARM
518            "ARM and Thumb is required"
542 void ARM::encodeAluGroup(uint8_t *loc, const Relocation &rel, uint64_t val,
604 void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
650     // BLX (always unconditional) instruction to an ARM Target, select an
689     // value of bit 0 of Val. With bit 0 == 0 denoting ARM, if the symbol is
691     // PLT entries are always ARM state so we know we need to interwork.
875 int64_t ARM::getImplicitAddend(const uint8_t *buf, RelType type) const {
944   // ELF for the ARM Architecture 4.6.1.1 the implicit addend for MOVW and
1020     // From ELF for the ARM Architecture the initial signed addend is formed
1053   for (auto &kv : static_cast<ARM &>(*ctx.target).sectionMap) {
1066   auto &sectionMap = static_cast<ARM &>(*ctx.target).sectionMap;
1092       static_cast<ARM &>(*sec->file->ctx.target).sectionMap[sec].push_back(sym);
1115   auto &sectionMap = static_cast<ARM &>(*ctx.target).sectionMap;
1543 void elf::setARMTargetInfo(Ctx &ctx) { ctx.target.reset(new ARM(ctx)); }