Lines Matching +full:0 +full:x1b0
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
11 #define FROM_0_TO_15 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
14 #define FROM_0_TO_31 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
186 sdc1 $f0, (4 * 36 + 8 * 0)($4)
203 sdc1 $f0, (4 * 36 + 8 * 0)($4)
239 or $2, $0, $0
274 or $2, $0, $0
284 teq $0, $0
304 PPC64_STR(0)
305 mflr 0
306 std 0, PPC64_OFFS_SRR0(3) // store lr as ssr0
314 lwz 4, 0(4) // Get the first instruction at the return address.
315 xoris 0, 4, 0xe841 // Is it reloading the TOC register "ld 2,40(1)"?
316 cmplwi 0, 0x28
317 bne 0, LnoR2Fix // No need to fix up r2 if it is not.
351 mfcr 0
352 std 0, PPC64_OFFS_CR(3)
353 mfxer 0
354 std 0, PPC64_OFFS_XER(3)
356 // LR value saved from the register is not used, initialize it to 0.
357 li 0, 0
359 mflr 0
361 std 0, PPC64_OFFS_LR(3)
362 mfctr 0
363 std 0, PPC64_OFFS_CTR(3)
364 mfvrsave 0
365 std 0, PPC64_OFFS_VRSAVE(3)
382 stxvd2x n, 0, 4 ;\
386 stxvd2x n, 0, 4 ;\
390 PPC64_STVS(0)
462 PPC64_STF(0)
504 stvx n, 0, 4 ;\
505 ld 5, 0(4) ;\
510 PPC64_STV_UNALIGNED(0)
546 li 3, 0 // return UNW_ESUCCESS
563 stw 0, 8(3)
564 mflr 0
565 stw 0, 0(3) // store lr as ssr0
573 lwz 4, 0(4) // Get the instruction at the return address.
574 xoris 0, 4, 0x8041 // Is it reloading the TOC register "lwz 2,20(1)"?
575 cmplwi 0, 0x14
576 bne 0, LnoR2Fix // No need to fix up r2 if it is not.
612 mfspr 0, 256
613 stw 0, 156(3)
616 mfcr 0
617 stw 0, 136(3)
619 // LR value from the register is not used, initialize it to 0.
620 li 0, 0
621 stw 0, 144(3)
624 mfctr 0
625 stw 0, 148(3)
629 stfd 0, 160(3)
667 rlwinm 4, 4, 0, 0, 27 // mask low 4-bits
671 stvx _vec, 0, 4 SEPARATOR \
672 lwz 5, 0(4) SEPARATOR \
681 SAVE_VECTOR_UNALIGNED( 0, 424+0x000)
682 SAVE_VECTOR_UNALIGNED( 1, 424+0x010)
683 SAVE_VECTOR_UNALIGNED( 2, 424+0x020)
684 SAVE_VECTOR_UNALIGNED( 3, 424+0x030)
685 SAVE_VECTOR_UNALIGNED( 4, 424+0x040)
686 SAVE_VECTOR_UNALIGNED( 5, 424+0x050)
687 SAVE_VECTOR_UNALIGNED( 6, 424+0x060)
688 SAVE_VECTOR_UNALIGNED( 7, 424+0x070)
689 SAVE_VECTOR_UNALIGNED( 8, 424+0x080)
690 SAVE_VECTOR_UNALIGNED( 9, 424+0x090)
691 SAVE_VECTOR_UNALIGNED(10, 424+0x0A0)
692 SAVE_VECTOR_UNALIGNED(11, 424+0x0B0)
693 SAVE_VECTOR_UNALIGNED(12, 424+0x0C0)
694 SAVE_VECTOR_UNALIGNED(13, 424+0x0D0)
695 SAVE_VECTOR_UNALIGNED(14, 424+0x0E0)
696 SAVE_VECTOR_UNALIGNED(15, 424+0x0F0)
697 SAVE_VECTOR_UNALIGNED(16, 424+0x100)
698 SAVE_VECTOR_UNALIGNED(17, 424+0x110)
699 SAVE_VECTOR_UNALIGNED(18, 424+0x120)
700 SAVE_VECTOR_UNALIGNED(19, 424+0x130)
701 SAVE_VECTOR_UNALIGNED(20, 424+0x140)
702 SAVE_VECTOR_UNALIGNED(21, 424+0x150)
703 SAVE_VECTOR_UNALIGNED(22, 424+0x160)
704 SAVE_VECTOR_UNALIGNED(23, 424+0x170)
705 SAVE_VECTOR_UNALIGNED(24, 424+0x180)
706 SAVE_VECTOR_UNALIGNED(25, 424+0x190)
707 SAVE_VECTOR_UNALIGNED(26, 424+0x1A0)
708 SAVE_VECTOR_UNALIGNED(27, 424+0x1B0)
709 SAVE_VECTOR_UNALIGNED(28, 424+0x1C0)
710 SAVE_VECTOR_UNALIGNED(29, 424+0x1D0)
711 SAVE_VECTOR_UNALIGNED(30, 424+0x1E0)
712 SAVE_VECTOR_UNALIGNED(31, 424+0x1F0)
715 li 3, 0 // return UNW_ESUCCESS
729 stp x0, x1, [x0, #0x000]
730 stp x2, x3, [x0, #0x010]
731 stp x4, x5, [x0, #0x020]
732 stp x6, x7, [x0, #0x030]
733 stp x8, x9, [x0, #0x040]
734 stp x10,x11, [x0, #0x050]
735 stp x12,x13, [x0, #0x060]
736 stp x14,x15, [x0, #0x070]
737 stp x16,x17, [x0, #0x080]
738 stp x18,x19, [x0, #0x090]
739 stp x20,x21, [x0, #0x0A0]
740 stp x22,x23, [x0, #0x0B0]
741 stp x24,x25, [x0, #0x0C0]
742 stp x26,x27, [x0, #0x0D0]
743 stp x28,x29, [x0, #0x0E0]
744 str x30, [x0, #0x0F0]
746 str x1, [x0, #0x0F8]
747 str x30, [x0, #0x100] // store return address as pc
749 #if defined(__ARM_FP) && __ARM_FP != 0
750 stp d0, d1, [x0, #0x110]
751 stp d2, d3, [x0, #0x120]
752 stp d4, d5, [x0, #0x130]
753 stp d6, d7, [x0, #0x140]
754 stp d8, d9, [x0, #0x150]
755 stp d10,d11, [x0, #0x160]
756 stp d12,d13, [x0, #0x170]
757 stp d14,d15, [x0, #0x180]
758 stp d16,d17, [x0, #0x190]
759 stp d18,d19, [x0, #0x1A0]
760 stp d20,d21, [x0, #0x1B0]
761 stp d22,d23, [x0, #0x1C0]
762 stp d24,d25, [x0, #0x1D0]
763 stp d26,d27, [x0, #0x1E0]
764 stp d28,d29, [x0, #0x1F0]
765 str d30, [x0, #0x200]
766 str d31, [x0, #0x208]
768 mov x0, #0 // return UNW_ESUCCESS
803 str r1, [r0, #0] @ r11
811 movs r0, #0 @ return UNW_ESUCCESS
820 mov r0, #0 @ return UNW_ESUCCESS
932 l.sw 0(r3), r0
1028 stx %g1, [%o0 + 0x08]
1029 stx %g2, [%o0 + 0x10]
1030 stx %g3, [%o0 + 0x18]
1031 stx %g4, [%o0 + 0x20]
1032 stx %g5, [%o0 + 0x28]
1033 stx %g6, [%o0 + 0x30]
1034 stx %g7, [%o0 + 0x38]
1035 stx %o0, [%o0 + 0x40]
1036 stx %o1, [%o0 + 0x48]
1037 stx %o2, [%o0 + 0x50]
1038 stx %o3, [%o0 + 0x58]
1039 stx %o4, [%o0 + 0x60]
1040 stx %o5, [%o0 + 0x68]
1041 stx %o6, [%o0 + 0x70]
1042 stx %o7, [%o0 + 0x78]
1043 stx %l0, [%o0 + 0x80]
1044 stx %l1, [%o0 + 0x88]
1045 stx %l2, [%o0 + 0x90]
1046 stx %l3, [%o0 + 0x98]
1047 stx %l4, [%o0 + 0xa0]
1048 stx %l5, [%o0 + 0xa8]
1049 stx %l6, [%o0 + 0xb0]
1050 stx %l7, [%o0 + 0xb8]
1051 stx %i0, [%o0 + 0xc0]
1052 stx %i1, [%o0 + 0xc8]
1053 stx %i2, [%o0 + 0xd0]
1054 stx %i3, [%o0 + 0xd8]
1055 stx %i4, [%o0 + 0xe0]
1056 stx %i5, [%o0 + 0xe8]
1057 stx %i6, [%o0 + 0xf0]
1058 stx %i7, [%o0 + 0xf8]
1066 ldx [%sp + 2047 + 0x78], %g5
1068 stx %g4, [%o0 + 0x100]
1084 std %g0, [%o0 + 0]
1112 ISTORE x1, (RISCV_ISIZE * 0)(a0) // store ra as pc
1127 li a0, 0 // return UNW_ESUCCESS
1145 stm %r0, %r1, 0(%r2)
1156 lghi %r2, 0