Lines Matching full:signed

2 …nt -triple x86_64-unknown-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,SIGNED
118 // SIGNED-LABEL: @sdiv_sasausa(
119 // SIGNED-NEXT:  entry:
120 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @sa, align 2
121 // SIGNED-NEXT:    [[TMP1:%.*]] = load i16, ptr @usa, align 2
122 // SIGNED-NEXT:    [[RESIZE:%.*]] = sext i16 [[TMP0]] to i17
123 // SIGNED-NEXT:    [[UPSCALE:%.*]] = shl i17 [[RESIZE]], 1
124 // SIGNED-NEXT:    [[RESIZE1:%.*]] = zext i16 [[TMP1]] to i17
125 // SIGNED-NEXT:    [[TMP2:%.*]] = call i17 @llvm.sdiv.fix.i17(i17 [[UPSCALE]], i17 [[RESIZE1]], i32…
126 // SIGNED-NEXT:    [[DOWNSCALE:%.*]] = ashr i17 [[TMP2]], 1
127 // SIGNED-NEXT:    [[RESIZE2:%.*]] = trunc i17 [[DOWNSCALE]] to i16
128 // SIGNED-NEXT:    store i16 [[RESIZE2]], ptr @sa, align 2
129 // SIGNED-NEXT:    ret void
143 // SIGNED-LABEL: @sdiv_asaua(
144 // SIGNED-NEXT:  entry:
145 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @sa, align 2
146 // SIGNED-NEXT:    [[TMP1:%.*]] = load i32, ptr @ua, align 4
147 // SIGNED-NEXT:    [[RESIZE:%.*]] = sext i16 [[TMP0]] to i33
148 // SIGNED-NEXT:    [[UPSCALE:%.*]] = shl i33 [[RESIZE]], 9
149 // SIGNED-NEXT:    [[RESIZE1:%.*]] = zext i32 [[TMP1]] to i33
150 // SIGNED-NEXT:    [[TMP2:%.*]] = call i33 @llvm.sdiv.fix.i33(i33 [[UPSCALE]], i33 [[RESIZE1]], i32…
151 // SIGNED-NEXT:    [[DOWNSCALE:%.*]] = ashr i33 [[TMP2]], 1
152 // SIGNED-NEXT:    [[RESIZE2:%.*]] = trunc i33 [[DOWNSCALE]] to i32
153 // SIGNED-NEXT:    store i32 [[RESIZE2]], ptr @a, align 4
154 // SIGNED-NEXT:    ret void
170 // SIGNED-LABEL: @sdiv_sasausf(
171 // SIGNED-NEXT:  entry:
172 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @sa, align 2
173 // SIGNED-NEXT:    [[TMP1:%.*]] = load i8, ptr @usf, align 1
174 // SIGNED-NEXT:    [[RESIZE:%.*]] = sext i16 [[TMP0]] to i17
175 // SIGNED-NEXT:    [[UPSCALE:%.*]] = shl i17 [[RESIZE]], 1
176 // SIGNED-NEXT:    [[RESIZE1:%.*]] = zext i8 [[TMP1]] to i17
177 // SIGNED-NEXT:    [[TMP2:%.*]] = call i17 @llvm.sdiv.fix.i17(i17 [[UPSCALE]], i17 [[RESIZE1]], i32…
178 // SIGNED-NEXT:    [[DOWNSCALE:%.*]] = ashr i17 [[TMP2]], 1
179 // SIGNED-NEXT:    [[RESIZE2:%.*]] = trunc i17 [[DOWNSCALE]] to i16
180 // SIGNED-NEXT:    store i16 [[RESIZE2]], ptr @sa, align 2
181 // SIGNED-NEXT:    ret void
196 // SIGNED-LABEL: @sdiv_sasaulf(
197 // SIGNED-NEXT:  entry:
198 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @sa, align 2
199 // SIGNED-NEXT:    [[TMP1:%.*]] = load i32, ptr @ulf, align 4
200 // SIGNED-NEXT:    [[RESIZE:%.*]] = sext i16 [[TMP0]] to i41
201 // SIGNED-NEXT:    [[UPSCALE:%.*]] = shl i41 [[RESIZE]], 25
202 // SIGNED-NEXT:    [[RESIZE1:%.*]] = zext i32 [[TMP1]] to i41
203 // SIGNED-NEXT:    [[TMP2:%.*]] = call i41 @llvm.sdiv.fix.i41(i41 [[UPSCALE]], i41 [[RESIZE1]], i32…
204 // SIGNED-NEXT:    [[DOWNSCALE:%.*]] = ashr i41 [[TMP2]], 25
205 // SIGNED-NEXT:    [[RESIZE2:%.*]] = trunc i41 [[DOWNSCALE]] to i16
206 // SIGNED-NEXT:    store i16 [[RESIZE2]], ptr @sa, align 2
207 // SIGNED-NEXT:    ret void
243 // SIGNED-LABEL: @udiv_usausausa(
244 // SIGNED-NEXT:  entry:
245 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @usa, align 2
246 // SIGNED-NEXT:    [[TMP1:%.*]] = load i16, ptr @usa, align 2
247 // SIGNED-NEXT:    [[TMP2:%.*]] = call i16 @llvm.udiv.fix.i16(i16 [[TMP0]], i16 [[TMP1]], i32 8)
248 // SIGNED-NEXT:    store i16 [[TMP2]], ptr @usa, align 2
249 // SIGNED-NEXT:    ret void
263 // SIGNED-LABEL: @udiv_uausaua(
264 // SIGNED-NEXT:  entry:
265 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @usa, align 2
266 // SIGNED-NEXT:    [[TMP1:%.*]] = load i32, ptr @ua, align 4
267 // SIGNED-NEXT:    [[RESIZE:%.*]] = zext i16 [[TMP0]] to i32
268 // SIGNED-NEXT:    [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
269 // SIGNED-NEXT:    [[TMP2:%.*]] = call i32 @llvm.udiv.fix.i32(i32 [[UPSCALE]], i32 [[TMP1]], i32 16)
270 // SIGNED-NEXT:    store i32 [[TMP2]], ptr @ua, align 4
271 // SIGNED-NEXT:    ret void
287 // SIGNED-LABEL: @udiv_usausausf(
288 // SIGNED-NEXT:  entry:
289 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @usa, align 2
290 // SIGNED-NEXT:    [[TMP1:%.*]] = load i8, ptr @usf, align 1
291 // SIGNED-NEXT:    [[RESIZE:%.*]] = zext i8 [[TMP1]] to i16
292 // SIGNED-NEXT:    [[TMP2:%.*]] = call i16 @llvm.udiv.fix.i16(i16 [[TMP0]], i16 [[RESIZE]], i32 8)
293 // SIGNED-NEXT:    store i16 [[TMP2]], ptr @usa, align 2
294 // SIGNED-NEXT:    ret void
309 // SIGNED-LABEL: @udiv_usausauf(
310 // SIGNED-NEXT:  entry:
311 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @usa, align 2
312 // SIGNED-NEXT:    [[TMP1:%.*]] = load i16, ptr @uf, align 2
313 // SIGNED-NEXT:    [[RESIZE:%.*]] = zext i16 [[TMP0]] to i24
314 // SIGNED-NEXT:    [[UPSCALE:%.*]] = shl i24 [[RESIZE]], 8
315 // SIGNED-NEXT:    [[RESIZE1:%.*]] = zext i16 [[TMP1]] to i24
316 // SIGNED-NEXT:    [[TMP2:%.*]] = call i24 @llvm.udiv.fix.i24(i24 [[UPSCALE]], i24 [[RESIZE1]], i32…
317 // SIGNED-NEXT:    [[DOWNSCALE:%.*]] = lshr i24 [[TMP2]], 8
318 // SIGNED-NEXT:    [[RESIZE2:%.*]] = trunc i24 [[DOWNSCALE]] to i16
319 // SIGNED-NEXT:    store i16 [[RESIZE2]], ptr @usa, align 2
320 // SIGNED-NEXT:    ret void
372 // SIGNED-LABEL: @int_usausai(
373 // SIGNED-NEXT:  entry:
374 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @usa, align 2
375 // SIGNED-NEXT:    [[TMP1:%.*]] = load i32, ptr @i, align 4
376 // SIGNED-NEXT:    [[RESIZE:%.*]] = zext i16 [[TMP0]] to i40
377 // SIGNED-NEXT:    [[RESIZE1:%.*]] = sext i32 [[TMP1]] to i40
378 // SIGNED-NEXT:    [[UPSCALE:%.*]] = shl i40 [[RESIZE1]], 8
379 // SIGNED-NEXT:    [[TMP2:%.*]] = call i40 @llvm.sdiv.fix.i40(i40 [[RESIZE]], i40 [[UPSCALE]], i32 …
380 // SIGNED-NEXT:    [[RESIZE2:%.*]] = trunc i40 [[TMP2]] to i16
381 // SIGNED-NEXT:    store i16 [[RESIZE2]], ptr @usa, align 2
382 // SIGNED-NEXT:    ret void
400 // SIGNED-LABEL: @int_usausaui(
401 // SIGNED-NEXT:  entry:
402 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @usa, align 2
403 // SIGNED-NEXT:    [[TMP1:%.*]] = load i32, ptr @ui, align 4
404 // SIGNED-NEXT:    [[RESIZE:%.*]] = zext i16 [[TMP0]] to i40
405 // SIGNED-NEXT:    [[RESIZE1:%.*]] = zext i32 [[TMP1]] to i40
406 // SIGNED-NEXT:    [[UPSCALE:%.*]] = shl i40 [[RESIZE1]], 8
407 // SIGNED-NEXT:    [[TMP2:%.*]] = call i40 @llvm.udiv.fix.i40(i40 [[RESIZE]], i40 [[UPSCALE]], i32 …
408 // SIGNED-NEXT:    [[RESIZE2:%.*]] = trunc i40 [[TMP2]] to i16
409 // SIGNED-NEXT:    store i16 [[RESIZE2]], ptr @usa, align 2
410 // SIGNED-NEXT:    ret void
478 // SIGNED-LABEL: @int_usauiusa(
479 // SIGNED-NEXT:  entry:
480 // SIGNED-NEXT:    [[TMP0:%.*]] = load i32, ptr @ui, align 4
481 // SIGNED-NEXT:    [[TMP1:%.*]] = load i16, ptr @usa, align 2
482 // SIGNED-NEXT:    [[RESIZE:%.*]] = zext i32 [[TMP0]] to i40
483 // SIGNED-NEXT:    [[UPSCALE:%.*]] = shl i40 [[RESIZE]], 8
484 // SIGNED-NEXT:    [[RESIZE1:%.*]] = zext i16 [[TMP1]] to i40
485 // SIGNED-NEXT:    [[TMP2:%.*]] = call i40 @llvm.udiv.fix.i40(i40 [[UPSCALE]], i40 [[RESIZE1]], i32…
486 // SIGNED-NEXT:    [[RESIZE2:%.*]] = trunc i40 [[TMP2]] to i16
487 // SIGNED-NEXT:    store i16 [[RESIZE2]], ptr @usa, align 2
488 // SIGNED-NEXT:    ret void
535 // SIGNED-LABEL: @sat_usasusausas(
536 // SIGNED-NEXT:  entry:
537 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @usa, align 2
538 // SIGNED-NEXT:    [[TMP1:%.*]] = load i16, ptr @usa_sat, align 2
539 // SIGNED-NEXT:    [[TMP2:%.*]] = call i16 @llvm.udiv.fix.sat.i16(i16 [[TMP0]], i16 [[TMP1]], i32 8)
540 // SIGNED-NEXT:    store i16 [[TMP2]], ptr @usa_sat, align 2
541 // SIGNED-NEXT:    ret void
557 // SIGNED-LABEL: @sat_uasuausas(
558 // SIGNED-NEXT:  entry:
559 // SIGNED-NEXT:    [[TMP0:%.*]] = load i32, ptr @ua, align 4
560 // SIGNED-NEXT:    [[TMP1:%.*]] = load i16, ptr @usa_sat, align 2
561 // SIGNED-NEXT:    [[RESIZE:%.*]] = zext i16 [[TMP1]] to i32
562 // SIGNED-NEXT:    [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
563 // SIGNED-NEXT:    [[TMP2:%.*]] = call i32 @llvm.udiv.fix.sat.i32(i32 [[TMP0]], i32 [[UPSCALE]], i3…
564 // SIGNED-NEXT:    store i32 [[TMP2]], ptr @ua_sat, align 4
565 // SIGNED-NEXT:    ret void
623 // SIGNED-LABEL: @sat_ufsufsufs(
624 // SIGNED-NEXT:  entry:
625 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @uf_sat, align 2
626 // SIGNED-NEXT:    [[TMP1:%.*]] = load i16, ptr @uf_sat, align 2
627 // SIGNED-NEXT:    [[TMP2:%.*]] = call i16 @llvm.udiv.fix.sat.i16(i16 [[TMP0]], i16 [[TMP1]], i32 1…
628 // SIGNED-NEXT:    store i16 [[TMP2]], ptr @uf_sat, align 2
629 // SIGNED-NEXT:    ret void
645 // SIGNED-LABEL: @sat_usasusasi(
646 // SIGNED-NEXT:  entry:
647 // SIGNED-NEXT:    [[TMP0:%.*]] = load i16, ptr @usa_sat, align 2
648 // SIGNED-NEXT:    [[TMP1:%.*]] = load i32, ptr @i, align 4
649 // SIGNED-NEXT:    [[RESIZE:%.*]] = zext i16 [[TMP0]] to i40
650 // SIGNED-NEXT:    [[RESIZE1:%.*]] = sext i32 [[TMP1]] to i40
651 // SIGNED-NEXT:    [[UPSCALE:%.*]] = shl i40 [[RESIZE1]], 8
652 // SIGNED-NEXT:    [[TMP2:%.*]] = call i40 @llvm.sdiv.fix.sat.i40(i40 [[RESIZE]], i40 [[UPSCALE]], …
653 // SIGNED-NEXT:    [[TMP3:%.*]] = icmp sgt i40 [[TMP2]], 65535
654 // SIGNED-NEXT:    [[SATMAX:%.*]] = select i1 [[TMP3]], i40 65535, i40 [[TMP2]]
655 // SIGNED-NEXT:    [[TMP4:%.*]] = icmp slt i40 [[SATMAX]], 0
656 // SIGNED-NEXT:    [[SATMIN:%.*]] = select i1 [[TMP4]], i40 0, i40 [[SATMAX]]
657 // SIGNED-NEXT:    [[RESIZE2:%.*]] = trunc i40 [[SATMIN]] to i16
658 // SIGNED-NEXT:    store i16 [[RESIZE2]], ptr @usa_sat, align 2
659 // SIGNED-NEXT:    ret void