Lines Matching defs:Addend
551 short test_InterlockedIncrement16(short volatile *Addend) {
552 return _InterlockedIncrement16(++Addend);
554 // CHECK: define{{.*}}i16 @test_InterlockedIncrement16(ptr{{.*}}%Addend){{.*}}{
555 // CHECK: %incdec.ptr = getelementptr inbounds nuw i8, ptr %Addend, {{i64|i32}} 2
561 long test_InterlockedIncrement(long volatile *Addend) {
562 return _InterlockedIncrement(++Addend);
564 // CHECK: define{{.*}}i32 @test_InterlockedIncrement(ptr{{.*}}%Addend){{.*}}{
565 // CHECK: %incdec.ptr = getelementptr inbounds nuw i8, ptr %Addend, {{i64|i32}} 4
571 short test_InterlockedDecrement16(short volatile *Addend) {
572 return _InterlockedDecrement16(Addend);
574 // CHECK: define{{.*}}i16 @test_InterlockedDecrement16(ptr{{.*}}%Addend){{.*}}{
575 // CHECK: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i16 1 seq_cst, align 2
580 long test_InterlockedDecrement(long volatile *Addend) {
581 return _InterlockedDecrement(Addend);
583 // CHECK: define{{.*}}i32 @test_InterlockedDecrement(ptr{{.*}}%Addend){{.*}}{
584 // CHECK: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 seq_cst, align 4
667 __int64 test_InterlockedIncrement64(__int64 volatile *Addend) {
668 return _InterlockedIncrement64(Addend);
670 // CHECK: define{{.*}}i64 @test_InterlockedIncrement64(ptr{{.*}}%Addend){{.*}}{
671 // CHECK: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i64 1 seq_cst, align 8
676 __int64 test_InterlockedDecrement64(__int64 volatile *Addend) {
677 return _InterlockedDecrement64(Addend);
679 // CHECK: define{{.*}}i64 @test_InterlockedDecrement64(ptr{{.*}}%Addend){{.*}}{
680 // CHECK: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i64 1 seq_cst, align 8
1303 short test_InterlockedIncrement16_acq(short volatile *Addend) {
1304 return _InterlockedIncrement16_acq(Addend);
1306 // CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedIncrement16_acq(ptr{{.*}}%Addend){{.*}}{
1307 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i16 1 acquire, align 2
1312 short test_InterlockedIncrement16_rel(short volatile *Addend) {
1313 return _InterlockedIncrement16_rel(Addend);
1315 // CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedIncrement16_rel(ptr{{.*}}%Addend){{.*}}{
1316 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i16 1 release, align 2
1321 short test_InterlockedIncrement16_nf(short volatile *Addend) {
1322 return _InterlockedIncrement16_nf(Addend);
1324 // CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedIncrement16_nf(ptr{{.*}}%Addend){{.*}}{
1325 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i16 1 monotonic, align 2
1330 long test_InterlockedIncrement_acq(long volatile *Addend) {
1331 return _InterlockedIncrement_acq(Addend);
1333 // CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedIncrement_acq(ptr{{.*}}%Addend){{.*}}{
1334 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i32 1 acquire, align 4
1339 long test_InterlockedIncrement_rel(long volatile *Addend) {
1340 return _InterlockedIncrement_rel(Addend);
1342 // CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedIncrement_rel(ptr{{.*}}%Addend){{.*}}{
1343 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i32 1 release, align 4
1348 long test_InterlockedIncrement_nf(long volatile *Addend) {
1349 return _InterlockedIncrement_nf(Addend);
1351 // CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedIncrement_nf(ptr{{.*}}%Addend){{.*}}{
1352 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i32 1 monotonic, align 4
1357 __int64 test_InterlockedIncrement64_acq(__int64 volatile *Addend) {
1358 return _InterlockedIncrement64_acq(Addend);
1360 // CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedIncrement64_acq(ptr{{.*}}%Addend){{.*}}{
1361 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i64 1 acquire, align 8
1366 __int64 test_InterlockedIncrement64_rel(__int64 volatile *Addend) {
1367 return _InterlockedIncrement64_rel(Addend);
1369 // CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedIncrement64_rel(ptr{{.*}}%Addend){{.*}}{
1370 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i64 1 release, align 8
1375 __int64 test_InterlockedIncrement64_nf(__int64 volatile *Addend) {
1376 return _InterlockedIncrement64_nf(Addend);
1378 // CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedIncrement64_nf(ptr{{.*}}%Addend){{.*}}{
1379 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw add ptr %Addend, i64 1 monotonic, align 8
1384 short test_InterlockedDecrement16_acq(short volatile *Addend) {
1385 return _InterlockedDecrement16_acq(Addend);
1387 // CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedDecrement16_acq(ptr{{.*}}%Addend){{.*}}{
1388 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i16 1 acquire, align 2
1393 short test_InterlockedDecrement16_rel(short volatile *Addend) {
1394 return _InterlockedDecrement16_rel(Addend);
1396 // CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedDecrement16_rel(ptr{{.*}}%Addend){{.*}}{
1397 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i16 1 release, align 2
1402 short test_InterlockedDecrement16_nf(short volatile *Addend) {
1403 return _InterlockedDecrement16_nf(Addend);
1405 // CHECK-ARM-ARM64: define{{.*}}i16 @test_InterlockedDecrement16_nf(ptr{{.*}}%Addend){{.*}}{
1406 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i16 1 monotonic, align 2
1411 long test_InterlockedDecrement_acq(long volatile *Addend) {
1412 return _InterlockedDecrement_acq(Addend);
1414 // CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedDecrement_acq(ptr{{.*}}%Addend){{.*}}{
1415 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 acquire, align 4
1420 long test_InterlockedDecrement_rel(long volatile *Addend) {
1421 return _InterlockedDecrement_rel(Addend);
1423 // CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedDecrement_rel(ptr{{.*}}%Addend){{.*}}{
1424 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 release, align 4
1429 long test_InterlockedDecrement_nf(long volatile *Addend) {
1430 return _InterlockedDecrement_nf(Addend);
1432 // CHECK-ARM-ARM64: define{{.*}}i32 @test_InterlockedDecrement_nf(ptr{{.*}}%Addend){{.*}}{
1433 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i32 1 monotonic, align 4
1438 __int64 test_InterlockedDecrement64_acq(__int64 volatile *Addend) {
1439 return _InterlockedDecrement64_acq(Addend);
1441 // CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedDecrement64_acq(ptr{{.*}}%Addend){{.*}}{
1442 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i64 1 acquire, align 8
1447 __int64 test_InterlockedDecrement64_rel(__int64 volatile *Addend) {
1448 return _InterlockedDecrement64_rel(Addend);
1450 // CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedDecrement64_rel(ptr{{.*}}%Addend){{.*}}{
1451 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i64 1 release, align 8
1456 __int64 test_InterlockedDecrement64_nf(__int64 volatile *Addend) {
1457 return _InterlockedDecrement64_nf(Addend);
1459 // CHECK-ARM-ARM64: define{{.*}}i64 @test_InterlockedDecrement64_nf(ptr{{.*}}%Addend){{.*}}{
1460 // CHECK-ARM-ARM64: [[TMP:%[0-9]+]] = atomicrmw sub ptr %Addend, i64 1 monotonic, align 8