Lines Matching defs:sl
18 volatile vector signed long long sl, sl2;
46 // CHECK-NEXT: store volatile <2 x i64> [[TMP6]], ptr @sl, align 8
68 sl = sl2;
93 // CHECK-NEXT: store volatile <2 x i64> [[TMP6]], ptr @sl, align 8
115 sl = +sl2;
138 // CHECK-NEXT: store volatile <2 x i64> [[SUB3]], ptr @sl, align 8
152 sl = -sl2;
464 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
467 // CHECK-NEXT: store volatile <2 x i64> [[ADD18]], ptr @sl, align 8
468 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
471 // CHECK-NEXT: store volatile <2 x i64> [[ADD19]], ptr @sl, align 8
475 // CHECK-NEXT: store volatile <2 x i64> [[ADD20]], ptr @sl, align 8
541 sl = sl + sl2;
542 sl = sl + bl2;
543 sl = bl + sl2;
610 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
612 // CHECK-NEXT: store volatile <2 x i64> [[ADD12]], ptr @sl, align 8
614 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
616 // CHECK-NEXT: store volatile <2 x i64> [[ADD13]], ptr @sl, align 8
664 sl += sl2;
665 sl += bl2;
752 // CHECK-NEXT: [[TMP36:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
755 // CHECK-NEXT: store volatile <2 x i64> [[SUB18]], ptr @sl, align 8
756 // CHECK-NEXT: [[TMP38:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
759 // CHECK-NEXT: store volatile <2 x i64> [[SUB19]], ptr @sl, align 8
763 // CHECK-NEXT: store volatile <2 x i64> [[SUB20]], ptr @sl, align 8
829 sl = sl - sl2;
830 sl = sl - bl2;
831 sl = bl - sl2;
898 // CHECK-NEXT: [[TMP25:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
900 // CHECK-NEXT: store volatile <2 x i64> [[SUB12]], ptr @sl, align 8
902 // CHECK-NEXT: [[TMP27:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
904 // CHECK-NEXT: store volatile <2 x i64> [[SUB13]], ptr @sl, align 8
952 sl -= sl2;
953 sl -= bl2;
992 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
995 // CHECK-NEXT: store volatile <2 x i64> [[MUL6]], ptr @sl, align 8
1025 sl = sl * sl2;
1062 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1064 // CHECK-NEXT: store volatile <2 x i64> [[MUL6]], ptr @sl, align 8
1094 sl *= sl2;
1130 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1133 // CHECK-NEXT: store volatile <2 x i64> [[DIV6]], ptr @sl, align 8
1163 sl = sl / sl2;
1200 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1202 // CHECK-NEXT: store volatile <2 x i64> [[DIV6]], ptr @sl, align 8
1232 sl /= sl2;
1268 // CHECK-NEXT: [[TMP12:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1271 // CHECK-NEXT: store volatile <2 x i64> [[REM6]], ptr @sl, align 8
1297 sl = sl % sl2;
1332 // CHECK-NEXT: [[TMP13:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1334 // CHECK-NEXT: store volatile <2 x i64> [[REM6]], ptr @sl, align 8
1360 sl %= sl2;
1399 // CHECK-NEXT: store volatile <2 x i64> [[NOT9]], ptr @sl, align 8
1431 sl = ~sl2;
1527 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1530 // CHECK-NEXT: store volatile <2 x i64> [[AND21]], ptr @sl, align 8
1531 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1534 // CHECK-NEXT: store volatile <2 x i64> [[AND22]], ptr @sl, align 8
1538 // CHECK-NEXT: store volatile <2 x i64> [[AND23]], ptr @sl, align 8
1611 sl = sl & sl2;
1612 sl = sl & bl2;
1613 sl = bl & sl2;
1692 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1694 // CHECK-NEXT: store volatile <2 x i64> [[AND15]], ptr @sl, align 8
1696 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1698 // CHECK-NEXT: store volatile <2 x i64> [[AND16]], ptr @sl, align 8
1753 sl &= sl2;
1754 sl &= bl2;
1853 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1856 // CHECK-NEXT: store volatile <2 x i64> [[OR21]], ptr @sl, align 8
1857 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
1860 // CHECK-NEXT: store volatile <2 x i64> [[OR22]], ptr @sl, align 8
1864 // CHECK-NEXT: store volatile <2 x i64> [[OR23]], ptr @sl, align 8
1937 sl = sl | sl2;
1938 sl = sl | bl2;
1939 sl = bl | sl2;
2018 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2020 // CHECK-NEXT: store volatile <2 x i64> [[OR15]], ptr @sl, align 8
2022 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2024 // CHECK-NEXT: store volatile <2 x i64> [[OR16]], ptr @sl, align 8
2079 sl |= sl2;
2080 sl |= bl2;
2179 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2182 // CHECK-NEXT: store volatile <2 x i64> [[XOR21]], ptr @sl, align 8
2183 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2186 // CHECK-NEXT: store volatile <2 x i64> [[XOR22]], ptr @sl, align 8
2190 // CHECK-NEXT: store volatile <2 x i64> [[XOR23]], ptr @sl, align 8
2263 sl = sl ^ sl2;
2264 sl = sl ^ bl2;
2265 sl = bl ^ sl2;
2344 // CHECK-NEXT: [[TMP31:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2346 // CHECK-NEXT: store volatile <2 x i64> [[XOR15]], ptr @sl, align 8
2348 // CHECK-NEXT: [[TMP33:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2350 // CHECK-NEXT: store volatile <2 x i64> [[XOR16]], ptr @sl, align 8
2405 sl ^= sl2;
2406 sl ^= bl2;
2527 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2530 // CHECK-NEXT: store volatile <2 x i64> [[SHL37]], ptr @sl, align 8
2531 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2534 // CHECK-NEXT: store volatile <2 x i64> [[SHL38]], ptr @sl, align 8
2535 // CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2541 // CHECK-NEXT: store volatile <2 x i64> [[SHL42]], ptr @sl, align 8
2542 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2544 // CHECK-NEXT: store volatile <2 x i64> [[SHL43]], ptr @sl, align 8
2630 sl = sl << sl2;
2631 sl = sl << ul2;
2632 sl = sl << cnt;
2633 sl = sl << 5;
2759 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2761 // CHECK-NEXT: store volatile <2 x i64> [[SHL37]], ptr @sl, align 8
2763 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2765 // CHECK-NEXT: store volatile <2 x i64> [[SHL38]], ptr @sl, align 8
2769 // CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2772 // CHECK-NEXT: store volatile <2 x i64> [[SHL42]], ptr @sl, align 8
2773 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2775 // CHECK-NEXT: store volatile <2 x i64> [[SHL43]], ptr @sl, align 8
2861 sl <<= sl2;
2862 sl <<= ul2;
2863 sl <<= cnt;
2864 sl <<= 5;
2989 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2992 // CHECK-NEXT: store volatile <2 x i64> [[SHR37]], ptr @sl, align 8
2993 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
2996 // CHECK-NEXT: store volatile <2 x i64> [[SHR38]], ptr @sl, align 8
2997 // CHECK-NEXT: [[TMP46:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3003 // CHECK-NEXT: store volatile <2 x i64> [[SHR42]], ptr @sl, align 8
3004 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3006 // CHECK-NEXT: store volatile <2 x i64> [[SHR43]], ptr @sl, align 8
3092 sl = sl >> sl2;
3093 sl = sl >> ul2;
3094 sl = sl >> cnt;
3095 sl = sl >> 5;
3221 // CHECK-NEXT: [[TMP43:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3223 // CHECK-NEXT: store volatile <2 x i64> [[SHR37]], ptr @sl, align 8
3225 // CHECK-NEXT: [[TMP45:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3227 // CHECK-NEXT: store volatile <2 x i64> [[SHR38]], ptr @sl, align 8
3231 // CHECK-NEXT: [[TMP47:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3234 // CHECK-NEXT: store volatile <2 x i64> [[SHR42]], ptr @sl, align 8
3235 // CHECK-NEXT: [[TMP48:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3237 // CHECK-NEXT: store volatile <2 x i64> [[SHR43]], ptr @sl, align 8
3323 sl >>= sl2;
3324 sl >>= ul2;
3325 sl >>= cnt;
3326 sl >>= 5;
3451 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3456 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3554 bl = sl == sl2;
3555 bl = sl == bl2;
3681 // CHECK-NEXT: [[TMP42:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3686 // CHECK-NEXT: [[TMP44:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3784 bl = sl != sl2;
3785 bl = sl != bl2;
3851 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
3902 bl = sl >= sl2;
3961 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
4012 bl = sl > sl2;
4071 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
4122 bl = sl <= sl2;
4181 // CHECK-NEXT: [[TMP18:%.*]] = load volatile <2 x i64>, ptr @sl, align 8
4232 bl = sl < sl2;