Lines Matching refs:vs2
23 vuint8mf8_t test_vclz_v_u8mf8_tu(vuint8mf8_t maskedoff, vuint8mf8_t vs2, size_t vl) {
24 return __riscv_vclz_tu(maskedoff, vs2, vl);
32 vuint8mf4_t test_vclz_v_u8mf4_tu(vuint8mf4_t maskedoff, vuint8mf4_t vs2, size_t vl) {
33 return __riscv_vclz_tu(maskedoff, vs2, vl);
41 vuint8mf2_t test_vclz_v_u8mf2_tu(vuint8mf2_t maskedoff, vuint8mf2_t vs2, size_t vl) {
42 return __riscv_vclz_tu(maskedoff, vs2, vl);
50 vuint8m1_t test_vclz_v_u8m1_tu(vuint8m1_t maskedoff, vuint8m1_t vs2, size_t vl) {
51 return __riscv_vclz_tu(maskedoff, vs2, vl);
59 vuint8m2_t test_vclz_v_u8m2_tu(vuint8m2_t maskedoff, vuint8m2_t vs2, size_t vl) {
60 return __riscv_vclz_tu(maskedoff, vs2, vl);
68 vuint8m4_t test_vclz_v_u8m4_tu(vuint8m4_t maskedoff, vuint8m4_t vs2, size_t vl) {
69 return __riscv_vclz_tu(maskedoff, vs2, vl);
77 vuint8m8_t test_vclz_v_u8m8_tu(vuint8m8_t maskedoff, vuint8m8_t vs2, size_t vl) {
78 return __riscv_vclz_tu(maskedoff, vs2, vl);
86 vuint16mf4_t test_vclz_v_u16mf4_tu(vuint16mf4_t maskedoff, vuint16mf4_t vs2, size_t vl) {
87 return __riscv_vclz_tu(maskedoff, vs2, vl);
95 vuint16mf2_t test_vclz_v_u16mf2_tu(vuint16mf2_t maskedoff, vuint16mf2_t vs2, size_t vl) {
96 return __riscv_vclz_tu(maskedoff, vs2, vl);
104 vuint16m1_t test_vclz_v_u16m1_tu(vuint16m1_t maskedoff, vuint16m1_t vs2, size_t vl) {
105 return __riscv_vclz_tu(maskedoff, vs2, vl);
113 vuint16m2_t test_vclz_v_u16m2_tu(vuint16m2_t maskedoff, vuint16m2_t vs2, size_t vl) {
114 return __riscv_vclz_tu(maskedoff, vs2, vl);
122 vuint16m4_t test_vclz_v_u16m4_tu(vuint16m4_t maskedoff, vuint16m4_t vs2, size_t vl) {
123 return __riscv_vclz_tu(maskedoff, vs2, vl);
131 vuint16m8_t test_vclz_v_u16m8_tu(vuint16m8_t maskedoff, vuint16m8_t vs2, size_t vl) {
132 return __riscv_vclz_tu(maskedoff, vs2, vl);
140 vuint32mf2_t test_vclz_v_u32mf2_tu(vuint32mf2_t maskedoff, vuint32mf2_t vs2, size_t vl) {
141 return __riscv_vclz_tu(maskedoff, vs2, vl);
149 vuint32m1_t test_vclz_v_u32m1_tu(vuint32m1_t maskedoff, vuint32m1_t vs2, size_t vl) {
150 return __riscv_vclz_tu(maskedoff, vs2, vl);
158 vuint32m2_t test_vclz_v_u32m2_tu(vuint32m2_t maskedoff, vuint32m2_t vs2, size_t vl) {
159 return __riscv_vclz_tu(maskedoff, vs2, vl);
167 vuint32m4_t test_vclz_v_u32m4_tu(vuint32m4_t maskedoff, vuint32m4_t vs2, size_t vl) {
168 return __riscv_vclz_tu(maskedoff, vs2, vl);
176 vuint32m8_t test_vclz_v_u32m8_tu(vuint32m8_t maskedoff, vuint32m8_t vs2, size_t vl) {
177 return __riscv_vclz_tu(maskedoff, vs2, vl);
185 vuint64m1_t test_vclz_v_u64m1_tu(vuint64m1_t maskedoff, vuint64m1_t vs2, size_t vl) {
186 return __riscv_vclz_tu(maskedoff, vs2, vl);
194 vuint64m2_t test_vclz_v_u64m2_tu(vuint64m2_t maskedoff, vuint64m2_t vs2, size_t vl) {
195 return __riscv_vclz_tu(maskedoff, vs2, vl);
203 vuint64m4_t test_vclz_v_u64m4_tu(vuint64m4_t maskedoff, vuint64m4_t vs2, size_t vl) {
204 return __riscv_vclz_tu(maskedoff, vs2, vl);
212 vuint64m8_t test_vclz_v_u64m8_tu(vuint64m8_t maskedoff, vuint64m8_t vs2, size_t vl) {
213 return __riscv_vclz_tu(maskedoff, vs2, vl);
221 vuint8mf8_t test_vclz_v_u8mf8_tum(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t vs2, size_t vl) {
222 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
230 vuint8mf4_t test_vclz_v_u8mf4_tum(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t vs2, size_t vl) {
231 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
239 vuint8mf2_t test_vclz_v_u8mf2_tum(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t vs2, size_t vl) {
240 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
248 vuint8m1_t test_vclz_v_u8m1_tum(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t vs2, size_t vl) {
249 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
257 vuint8m2_t test_vclz_v_u8m2_tum(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t vs2, size_t vl) {
258 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
266 vuint8m4_t test_vclz_v_u8m4_tum(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t vs2, size_t vl) {
267 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
275 vuint8m8_t test_vclz_v_u8m8_tum(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t vs2, size_t vl) {
276 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
284 vuint16mf4_t test_vclz_v_u16mf4_tum(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t vs2, size_t vl) {
285 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
293 vuint16mf2_t test_vclz_v_u16mf2_tum(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t vs2, size_t vl) {
294 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
302 vuint16m1_t test_vclz_v_u16m1_tum(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t vs2, size_t vl) {
303 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
311 vuint16m2_t test_vclz_v_u16m2_tum(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t vs2, size_t vl) {
312 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
320 vuint16m4_t test_vclz_v_u16m4_tum(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t vs2, size_t vl) {
321 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
329 vuint16m8_t test_vclz_v_u16m8_tum(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t vs2, size_t vl) {
330 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
338 vuint32mf2_t test_vclz_v_u32mf2_tum(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t vs2, size_t vl) {
339 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
347 vuint32m1_t test_vclz_v_u32m1_tum(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t vs2, size_t vl) {
348 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
356 vuint32m2_t test_vclz_v_u32m2_tum(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t vs2, size_t vl) {
357 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
365 vuint32m4_t test_vclz_v_u32m4_tum(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t vs2, size_t vl) {
366 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
374 vuint32m8_t test_vclz_v_u32m8_tum(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t vs2, size_t vl) {
375 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
383 vuint64m1_t test_vclz_v_u64m1_tum(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, size_t vl) {
384 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
392 vuint64m2_t test_vclz_v_u64m2_tum(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, size_t vl) {
393 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
401 vuint64m4_t test_vclz_v_u64m4_tum(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, size_t vl) {
402 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
410 vuint64m8_t test_vclz_v_u64m8_tum(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, size_t vl) {
411 return __riscv_vclz_tum(mask, maskedoff, vs2, vl);
419 vuint8mf8_t test_vclz_v_u8mf8_tumu(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t vs2, size_t vl) {
420 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
428 vuint8mf4_t test_vclz_v_u8mf4_tumu(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t vs2, size_t vl) {
429 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
437 vuint8mf2_t test_vclz_v_u8mf2_tumu(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t vs2, size_t vl) {
438 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
446 vuint8m1_t test_vclz_v_u8m1_tumu(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t vs2, size_t vl) {
447 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
455 vuint8m2_t test_vclz_v_u8m2_tumu(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t vs2, size_t vl) {
456 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
464 vuint8m4_t test_vclz_v_u8m4_tumu(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t vs2, size_t vl) {
465 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
473 vuint8m8_t test_vclz_v_u8m8_tumu(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t vs2, size_t vl) {
474 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
482 vuint16mf4_t test_vclz_v_u16mf4_tumu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t vs2, size_t vl) {
483 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
491 vuint16mf2_t test_vclz_v_u16mf2_tumu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t vs2, size_t vl) {
492 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
500 vuint16m1_t test_vclz_v_u16m1_tumu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t vs2, size_t vl) {
501 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
509 vuint16m2_t test_vclz_v_u16m2_tumu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t vs2, size_t vl) {
510 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
518 vuint16m4_t test_vclz_v_u16m4_tumu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t vs2, size_t vl) {
519 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
527 vuint16m8_t test_vclz_v_u16m8_tumu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t vs2, size_t vl) {
528 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
536 vuint32mf2_t test_vclz_v_u32mf2_tumu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t vs2, size_t vl) {
537 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
545 vuint32m1_t test_vclz_v_u32m1_tumu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t vs2, size_t vl) {
546 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
554 vuint32m2_t test_vclz_v_u32m2_tumu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t vs2, size_t vl) {
555 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
563 vuint32m4_t test_vclz_v_u32m4_tumu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t vs2, size_t vl) {
564 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
572 vuint32m8_t test_vclz_v_u32m8_tumu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t vs2, size_t vl) {
573 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
581 vuint64m1_t test_vclz_v_u64m1_tumu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, size_t vl) {
582 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
590 vuint64m2_t test_vclz_v_u64m2_tumu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, size_t vl) {
591 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
599 vuint64m4_t test_vclz_v_u64m4_tumu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, size_t vl) {
600 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
608 vuint64m8_t test_vclz_v_u64m8_tumu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, size_t vl) {
609 return __riscv_vclz_tumu(mask, maskedoff, vs2, vl);
617 vuint8mf8_t test_vclz_v_u8mf8_mu(vbool64_t mask, vuint8mf8_t maskedoff, vuint8mf8_t vs2, size_t vl) {
618 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
626 vuint8mf4_t test_vclz_v_u8mf4_mu(vbool32_t mask, vuint8mf4_t maskedoff, vuint8mf4_t vs2, size_t vl) {
627 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
635 vuint8mf2_t test_vclz_v_u8mf2_mu(vbool16_t mask, vuint8mf2_t maskedoff, vuint8mf2_t vs2, size_t vl) {
636 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
644 vuint8m1_t test_vclz_v_u8m1_mu(vbool8_t mask, vuint8m1_t maskedoff, vuint8m1_t vs2, size_t vl) {
645 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
653 vuint8m2_t test_vclz_v_u8m2_mu(vbool4_t mask, vuint8m2_t maskedoff, vuint8m2_t vs2, size_t vl) {
654 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
662 vuint8m4_t test_vclz_v_u8m4_mu(vbool2_t mask, vuint8m4_t maskedoff, vuint8m4_t vs2, size_t vl) {
663 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
671 vuint8m8_t test_vclz_v_u8m8_mu(vbool1_t mask, vuint8m8_t maskedoff, vuint8m8_t vs2, size_t vl) {
672 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
680 vuint16mf4_t test_vclz_v_u16mf4_mu(vbool64_t mask, vuint16mf4_t maskedoff, vuint16mf4_t vs2, size_t vl) {
681 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
689 vuint16mf2_t test_vclz_v_u16mf2_mu(vbool32_t mask, vuint16mf2_t maskedoff, vuint16mf2_t vs2, size_t vl) {
690 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
698 vuint16m1_t test_vclz_v_u16m1_mu(vbool16_t mask, vuint16m1_t maskedoff, vuint16m1_t vs2, size_t vl) {
699 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
707 vuint16m2_t test_vclz_v_u16m2_mu(vbool8_t mask, vuint16m2_t maskedoff, vuint16m2_t vs2, size_t vl) {
708 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
716 vuint16m4_t test_vclz_v_u16m4_mu(vbool4_t mask, vuint16m4_t maskedoff, vuint16m4_t vs2, size_t vl) {
717 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
725 vuint16m8_t test_vclz_v_u16m8_mu(vbool2_t mask, vuint16m8_t maskedoff, vuint16m8_t vs2, size_t vl) {
726 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
734 vuint32mf2_t test_vclz_v_u32mf2_mu(vbool64_t mask, vuint32mf2_t maskedoff, vuint32mf2_t vs2, size_t vl) {
735 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
743 vuint32m1_t test_vclz_v_u32m1_mu(vbool32_t mask, vuint32m1_t maskedoff, vuint32m1_t vs2, size_t vl) {
744 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
752 vuint32m2_t test_vclz_v_u32m2_mu(vbool16_t mask, vuint32m2_t maskedoff, vuint32m2_t vs2, size_t vl) {
753 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
761 vuint32m4_t test_vclz_v_u32m4_mu(vbool8_t mask, vuint32m4_t maskedoff, vuint32m4_t vs2, size_t vl) {
762 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
770 vuint32m8_t test_vclz_v_u32m8_mu(vbool4_t mask, vuint32m8_t maskedoff, vuint32m8_t vs2, size_t vl) {
771 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
779 vuint64m1_t test_vclz_v_u64m1_mu(vbool64_t mask, vuint64m1_t maskedoff, vuint64m1_t vs2, size_t vl) {
780 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
788 vuint64m2_t test_vclz_v_u64m2_mu(vbool32_t mask, vuint64m2_t maskedoff, vuint64m2_t vs2, size_t vl) {
789 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
797 vuint64m4_t test_vclz_v_u64m4_mu(vbool16_t mask, vuint64m4_t maskedoff, vuint64m4_t vs2, size_t vl) {
798 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);
806 vuint64m8_t test_vclz_v_u64m8_mu(vbool8_t mask, vuint64m8_t maskedoff, vuint64m8_t vs2, size_t vl) {
807 return __riscv_vclz_mu(mask, maskedoff, vs2, vl);