Lines Matching refs:vs2
23 vuint8mf8_t test_vcpop_v_u8mf8(vuint8mf8_t vs2, size_t vl) {
24 return __riscv_vcpop_v_u8mf8(vs2, vl);
32 vuint8mf4_t test_vcpop_v_u8mf4(vuint8mf4_t vs2, size_t vl) {
33 return __riscv_vcpop_v_u8mf4(vs2, vl);
41 vuint8mf2_t test_vcpop_v_u8mf2(vuint8mf2_t vs2, size_t vl) {
42 return __riscv_vcpop_v_u8mf2(vs2, vl);
50 vuint8m1_t test_vcpop_v_u8m1(vuint8m1_t vs2, size_t vl) {
51 return __riscv_vcpop_v_u8m1(vs2, vl);
59 vuint8m2_t test_vcpop_v_u8m2(vuint8m2_t vs2, size_t vl) {
60 return __riscv_vcpop_v_u8m2(vs2, vl);
68 vuint8m4_t test_vcpop_v_u8m4(vuint8m4_t vs2, size_t vl) {
69 return __riscv_vcpop_v_u8m4(vs2, vl);
77 vuint8m8_t test_vcpop_v_u8m8(vuint8m8_t vs2, size_t vl) {
78 return __riscv_vcpop_v_u8m8(vs2, vl);
86 vuint16mf4_t test_vcpop_v_u16mf4(vuint16mf4_t vs2, size_t vl) {
87 return __riscv_vcpop_v_u16mf4(vs2, vl);
95 vuint16mf2_t test_vcpop_v_u16mf2(vuint16mf2_t vs2, size_t vl) {
96 return __riscv_vcpop_v_u16mf2(vs2, vl);
104 vuint16m1_t test_vcpop_v_u16m1(vuint16m1_t vs2, size_t vl) {
105 return __riscv_vcpop_v_u16m1(vs2, vl);
113 vuint16m2_t test_vcpop_v_u16m2(vuint16m2_t vs2, size_t vl) {
114 return __riscv_vcpop_v_u16m2(vs2, vl);
122 vuint16m4_t test_vcpop_v_u16m4(vuint16m4_t vs2, size_t vl) {
123 return __riscv_vcpop_v_u16m4(vs2, vl);
131 vuint16m8_t test_vcpop_v_u16m8(vuint16m8_t vs2, size_t vl) {
132 return __riscv_vcpop_v_u16m8(vs2, vl);
140 vuint32mf2_t test_vcpop_v_u32mf2(vuint32mf2_t vs2, size_t vl) {
141 return __riscv_vcpop_v_u32mf2(vs2, vl);
149 vuint32m1_t test_vcpop_v_u32m1(vuint32m1_t vs2, size_t vl) {
150 return __riscv_vcpop_v_u32m1(vs2, vl);
158 vuint32m2_t test_vcpop_v_u32m2(vuint32m2_t vs2, size_t vl) {
159 return __riscv_vcpop_v_u32m2(vs2, vl);
167 vuint32m4_t test_vcpop_v_u32m4(vuint32m4_t vs2, size_t vl) {
168 return __riscv_vcpop_v_u32m4(vs2, vl);
176 vuint32m8_t test_vcpop_v_u32m8(vuint32m8_t vs2, size_t vl) {
177 return __riscv_vcpop_v_u32m8(vs2, vl);
185 vuint64m1_t test_vcpop_v_u64m1(vuint64m1_t vs2, size_t vl) {
186 return __riscv_vcpop_v_u64m1(vs2, vl);
194 vuint64m2_t test_vcpop_v_u64m2(vuint64m2_t vs2, size_t vl) {
195 return __riscv_vcpop_v_u64m2(vs2, vl);
203 vuint64m4_t test_vcpop_v_u64m4(vuint64m4_t vs2, size_t vl) {
204 return __riscv_vcpop_v_u64m4(vs2, vl);
212 vuint64m8_t test_vcpop_v_u64m8(vuint64m8_t vs2, size_t vl) {
213 return __riscv_vcpop_v_u64m8(vs2, vl);
221 vuint8mf8_t test_vcpop_v_u8mf8_m(vbool64_t mask, vuint8mf8_t vs2, size_t vl) {
222 return __riscv_vcpop_v_u8mf8_m(mask, vs2, vl);
230 vuint8mf4_t test_vcpop_v_u8mf4_m(vbool32_t mask, vuint8mf4_t vs2, size_t vl) {
231 return __riscv_vcpop_v_u8mf4_m(mask, vs2, vl);
239 vuint8mf2_t test_vcpop_v_u8mf2_m(vbool16_t mask, vuint8mf2_t vs2, size_t vl) {
240 return __riscv_vcpop_v_u8mf2_m(mask, vs2, vl);
248 vuint8m1_t test_vcpop_v_u8m1_m(vbool8_t mask, vuint8m1_t vs2, size_t vl) {
249 return __riscv_vcpop_v_u8m1_m(mask, vs2, vl);
257 vuint8m2_t test_vcpop_v_u8m2_m(vbool4_t mask, vuint8m2_t vs2, size_t vl) {
258 return __riscv_vcpop_v_u8m2_m(mask, vs2, vl);
266 vuint8m4_t test_vcpop_v_u8m4_m(vbool2_t mask, vuint8m4_t vs2, size_t vl) {
267 return __riscv_vcpop_v_u8m4_m(mask, vs2, vl);
275 vuint8m8_t test_vcpop_v_u8m8_m(vbool1_t mask, vuint8m8_t vs2, size_t vl) {
276 return __riscv_vcpop_v_u8m8_m(mask, vs2, vl);
284 vuint16mf4_t test_vcpop_v_u16mf4_m(vbool64_t mask, vuint16mf4_t vs2, size_t vl) {
285 return __riscv_vcpop_v_u16mf4_m(mask, vs2, vl);
293 vuint16mf2_t test_vcpop_v_u16mf2_m(vbool32_t mask, vuint16mf2_t vs2, size_t vl) {
294 return __riscv_vcpop_v_u16mf2_m(mask, vs2, vl);
302 vuint16m1_t test_vcpop_v_u16m1_m(vbool16_t mask, vuint16m1_t vs2, size_t vl) {
303 return __riscv_vcpop_v_u16m1_m(mask, vs2, vl);
311 vuint16m2_t test_vcpop_v_u16m2_m(vbool8_t mask, vuint16m2_t vs2, size_t vl) {
312 return __riscv_vcpop_v_u16m2_m(mask, vs2, vl);
320 vuint16m4_t test_vcpop_v_u16m4_m(vbool4_t mask, vuint16m4_t vs2, size_t vl) {
321 return __riscv_vcpop_v_u16m4_m(mask, vs2, vl);
329 vuint16m8_t test_vcpop_v_u16m8_m(vbool2_t mask, vuint16m8_t vs2, size_t vl) {
330 return __riscv_vcpop_v_u16m8_m(mask, vs2, vl);
338 vuint32mf2_t test_vcpop_v_u32mf2_m(vbool64_t mask, vuint32mf2_t vs2, size_t vl) {
339 return __riscv_vcpop_v_u32mf2_m(mask, vs2, vl);
347 vuint32m1_t test_vcpop_v_u32m1_m(vbool32_t mask, vuint32m1_t vs2, size_t vl) {
348 return __riscv_vcpop_v_u32m1_m(mask, vs2, vl);
356 vuint32m2_t test_vcpop_v_u32m2_m(vbool16_t mask, vuint32m2_t vs2, size_t vl) {
357 return __riscv_vcpop_v_u32m2_m(mask, vs2, vl);
365 vuint32m4_t test_vcpop_v_u32m4_m(vbool8_t mask, vuint32m4_t vs2, size_t vl) {
366 return __riscv_vcpop_v_u32m4_m(mask, vs2, vl);
374 vuint32m8_t test_vcpop_v_u32m8_m(vbool4_t mask, vuint32m8_t vs2, size_t vl) {
375 return __riscv_vcpop_v_u32m8_m(mask, vs2, vl);
383 vuint64m1_t test_vcpop_v_u64m1_m(vbool64_t mask, vuint64m1_t vs2, size_t vl) {
384 return __riscv_vcpop_v_u64m1_m(mask, vs2, vl);
392 vuint64m2_t test_vcpop_v_u64m2_m(vbool32_t mask, vuint64m2_t vs2, size_t vl) {
393 return __riscv_vcpop_v_u64m2_m(mask, vs2, vl);
401 vuint64m4_t test_vcpop_v_u64m4_m(vbool16_t mask, vuint64m4_t vs2, size_t vl) {
402 return __riscv_vcpop_v_u64m4_m(mask, vs2, vl);
410 vuint64m8_t test_vcpop_v_u64m8_m(vbool8_t mask, vuint64m8_t vs2, size_t vl) {
411 return __riscv_vcpop_v_u64m8_m(mask, vs2, vl);