Lines Matching +full:zero +full:- +full:point
1 // RUN: %clang_cc1 -triple loongarch64 -target-feature +f -target-feature +d -target-abi lp64d \
2 // RUN: -emit-llvm %s -o - | FileCheck %s
12 /// In most cases, the unsigned integer data types are zero-extended when stored
13 /// in general-purpose register, and the signed integer data types are
14 /// sign-extended. However, in the LP64D ABI, unsigned 32-bit types, such as
15 /// unsigned int, are stored in general-purpose registers as proper sign
16 /// extensions of their 32-bit values.
18 // CHECK-LABEL: define{{.*}} zeroext i1 @check_bool()
21 // CHECK-LABEL: define{{.*}} signext i8 @check_char()
24 // CHECK-LABEL: define{{.*}} signext i16 @check_short()
27 // CHECK-LABEL: define{{.*}} signext i32 @check_int()
30 // CHECK-LABEL: define{{.*}} i64 @check_long()
33 // CHECK-LABEL: define{{.*}} i64 @check_longlong()
36 // CHECK-LABEL: define{{.*}} zeroext i8 @check_uchar()
39 // CHECK-LABEL: define{{.*}} zeroext i16 @check_ushort()
42 // CHECK-LABEL: define{{.*}} signext i32 @check_uint()
45 // CHECK-LABEL: define{{.*}} i64 @check_ulong()
48 // CHECK-LABEL: define{{.*}} i64 @check_ulonglong()
51 // CHECK-LABEL: define{{.*}} float @check_float()
54 // CHECK-LABEL: define{{.*}} double @check_double()
57 // CHECK-LABEL: define{{.*}} fp128 @check_longdouble()
65 /// i. If the argument is floating-point type, the argument is passed in FAR. if
68 /// floating-point types narrower than GRLEN bits are widened to GRLEN bits,
73 /// bits are zero-extended to GRLEN bits, and the signed integer scalars are
74 /// sign-extended.
76 /// a. The argument is passed in a pair of GAR, with the low-order GRLEN bits in
77 /// the lower-numbered register and the high-order GRLEN bits in the
78 /// higher-numbered register. If exactly one register is available, the
79 /// low-order GRLEN bits are passed in the register and the high-order GRLEN
84 /// only check the correctness of argument (or return value)'s sign/zero
87 // CHECK-LABEL: define{{.*}} signext i32 @f_scalar(i1 noundef zeroext %a, i8 noundef signext %b, i8…
97 /// non-standard extension(same as union arguments and return values). Bits
106 // CHECK-LABEL: define{{.*}} void @f_empty_s()
112 /// a. The structure has only fixed-point members. If there is an available GAR,
120 // CHECK-LABEL: define{{.*}} i64 @f_i16x4_s(i64 %x.coerce)
125 /// b. The structure has only floating-point members:
126 /// i. One floating-point member. The argument is passed in a FAR; If no FAR is
138 // CHECK-LABEL: define{{.*}} float @f_f32x1_s(float %0)
143 // CHECK-LABEL: define{{.*}} double @f_f64x1_s(double %0)
148 /// ii. Two floating-point members. The argument is passed in a pair of
149 /// available FAR, with the low-order float member bits in the lower-numbered
150 /// FAR and the high-order float member bits in the higher-numbered FAR. If the
158 // CHECK-LABEL: define{{.*}} { float, float } @f_f32x2_s(float %0, float %1)
163 /// c. The structure has both fixed-point and floating-point members, i.e. the
165 /// i. Multiple fixed-point members. If there are available GAR, the structure
173 // CHECK-LABEL: define{{.*}} i64 @f_f32x1_i16x2_s(i64 %x.coerce)
178 /// ii. Only one fixed-point member. If one FAR and one GAR are available, the
179 /// floating-point member of the structure is passed in the FAR, and the integer
180 /// member of the structure is passed in the GAR; If no floating-point register
189 // CHECK-LABEL: define{{.*}} { float, i32 } @f_f32x1_i32x1_s(float %0, i32 %1)
195 /// a. Only fixed-point members.
196 /// i. The argument is passed in a pair of available GAR, with the low-order
197 /// bits in the lower-numbered GAR and the high-order bits in the
198 /// higher-numbered GAR. If only one GAR is available, the low-order bits are in
199 /// the GAR and the high-order bits are on the stack, and passed on the stack if
206 // CHECK-LABEL: define{{.*}} [2 x i64] @f_i64x2_s([2 x i64] %x.coerce)
211 /// b. Only floating-point members.
213 /// adjacent float members or 3-4 float members. The argument is passed in a
214 /// pair of available GAR, with the low-order bits in the lower-numbered GAR and
215 /// the high-order bits in the higher-numbered GAR. If only one GAR is
216 /// available, the low-order bits are in the GAR and the high-order bits are on
223 // CHECK-LABEL: define{{.*}} i128 @f_f128x1_s(i128 %x.coerce)
233 // CHECK-LABEL: define{{.*}} [2 x i64] @f_f64x1_f32x2_s([2 x i64] %x.coerce)
242 // CHECK-LABEL: define{{.*}} [2 x i64] @f_f32x3_s([2 x i64] %x.coerce)
251 // CHECK-LABEL: define{{.*}} [2 x i64] @f_f32x4_s([2 x i64] %x.coerce)
264 // CHECK-LABEL: define{{.*}} { double, double } @f_f64x2_s(double %0, double %1)
269 /// c. Both fixed-point and floating-point members.
270 /// i. The structure has one double member and only one fixed-point member.
271 /// A. If one FAR and one GAR are available, the floating-point member of the
273 /// passed in the GAR; If no floating-point registers but two GARs are
275 /// low-order bits are in the GAR and the high-order bits are on the stack; And
283 // CHECK-LABEL: define{{.*}} { double, i64 } @f_f64x1_i64x1_s(double %0, i64 %1)
289 /// A. The argument is passed in a pair of available GAR, with the low-order
290 /// bits in the lower-numbered GAR and the high-order bits in the
291 /// higher-numbered GAR. If only one GAR is available, the low-order bits are in
292 /// the GAR and the high-order bits are on the stack, and passed on the stack if
300 // CHECK-LABEL: define{{.*}} [2 x i64] @f_f64x1_i32x2_s([2 x i64] %x.coerce)
310 // CHECK-LABEL: define{{.*}} [2 x i64] @f_f32x2_i32x2_s([2 x i64] %x.coerce)
324 // CHECK-LABEL: define{{.*}} void @f_i64x4_s(ptr{{.*}} sret(%struct.i64x4_s) align 8 %agg.result, p…
333 // CHECK-LABEL: define{{.*}} void @f_f64x4_s(ptr{{.*}} sret(%struct.f64x4_s) align 8 %agg.result, p…
344 // CHECK-LABEL: define{{.*}} void @f_empty_u()
359 // CHECK-LABEL: define{{.*}} i64 @f_i32_f32_u(i64 %x.coerce)
369 // CHECK-LABEL: define{{.*}} i64 @f_i64_f64_u(i64 %x.coerce)
375 /// a. The argument is passed in a pair of available GAR, with the low-order
376 /// bits in the lower-numbered GAR and the high-order bits in the
377 /// higher-numbered GAR. If only one GAR is available, the low-order bits are in
378 /// the GAR and the high-order bits are on the stack. The arguments are passed
386 // CHECK-LABEL: define{{.*}} i128 @f_i128_f128_u(i128 %x.coerce)
400 // CHECK-LABEL: define{{.*}} void @f_i64_arr3_u(ptr{{.*}} sret(%union.i64_arr3_u) align 8 %agg.resu…
407 /// A complex floating-point number, or a structure containing just one complex
408 /// floating-point number, is passed as though it were a structure containing
409 /// two floating-point reals.
411 // CHECK-LABEL: define{{.*}} { float, float } @f_floatcomplex(float noundef %x.coerce0, float nound…
414 // CHECK-LABEL: define{{.*}} { double, double } @f_doublecomplex(double noundef %x.coerce0, double …
420 // CHECK-LABEL: define{{.*}} { float, float } @f_floatcomplex_s(float %0, float %1)
428 // CHECK-LABEL: define{{.*}} { double, double } @f_doublecomplex_s(double %0, double %1)
439 // CHECK-LABEL: define{{.*}} void @f_va_caller()
446 // CHECK-LABEL: @f_va_int(
447 // CHECK-NEXT: entry:
448 // CHECK-NEXT: [[FMT_ADDR:%.*]] = alloca ptr, align 8
449 // CHECK-NEXT: [[VA:%.*]] = alloca ptr, align 8
450 // CHECK-NEXT: [[V:%.*]] = alloca i32, align 4
451 // CHECK-NEXT: store ptr [[FMT:%.*]], ptr [[FMT_ADDR]], align 8
452 // CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VA]])
453 // CHECK-NEXT: [[ARGP_CUR:%.*]] = load ptr, ptr [[VA]], align 8
454 // CHECK-NEXT: [[ARGP_NEXT:%.*]] = getelementptr inbounds i8, ptr [[ARGP_CUR]], i64 8
455 // CHECK-NEXT: store ptr [[ARGP_NEXT]], ptr [[VA]], align 8
456 // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARGP_CUR]], align 8
457 // CHECK-NEXT: store i32 [[TMP0]], ptr [[V]], align 4
458 // CHECK-NEXT: call void @llvm.va_end.p0(ptr [[VA]])
459 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[V]], align 4
460 // CHECK-NEXT: ret i32 [[TMP1]]
469 /// Part 6. Structures with zero size fields (bitfields or arrays).
471 /// Check that zero size fields in structure are ignored.
484 // CHECK-LABEL: define{{.*}} { double, double } @f_f64x2_zsfs_s(double %0, double %1)