Lines Matching defs:SSE
39 /// Returns true if this type can be passed in SSE registers with the
61 /// Returns true if this aggregate is small enough to be passed in SSE registers
586 // Otherwise, if the type contains an SSE vector type, the alignment is 16.
918 // Since MSVC 2015, the first three SSE vectors have been passed in
1202 SSE,
1225 /// final MEMORY or SSE classes when necessary.
1312 /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to
1721 // eightbyte isn't SSE or any other eightbyte isn't SSEUP, the whole
1725 // (d) If SSEUP is not preceded by SSE or SSEUP, it is converted to SSE.
1737 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp))
1739 if (Hi == SSEUp && Lo != SSE)
1740 Hi = SSE;
1763 // (f) Otherwise class SSE is used.
1780 return SSE;
1810 Current = SSE;
1812 Lo = SSE;
1817 Lo = SSE;
1823 Current = SSE;
1827 // FIXME: _Decimal32 and _Decimal64 are SSE.
1828 // FIXME: _float128 and _Decimal128 are (SSE, SSEUp).
1888 // gcc passes <1 x long long> as SSE but clang used to unconditionally
1898 Current = SSE;
1915 // least significant one belongs to class SSE and all the others to class
1927 // split into eight eightbyte chunks, one SSE and seven SSEUP.
1928 Lo = SSE;
1945 Current = SSE;
1947 Lo = Hi = SSE;
1955 Lo = Hi = SSE;
2022 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp array classification.");
2402 /// low 8 bytes of an XMM register, corresponding to the SSE class.
2579 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2588 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2619 // AMD64-ABI 3.2.3p4: Rule 4. If the class is SSE, the next
2620 // available SSE register of the sequence %xmm0, %xmm1 is used.
2621 case SSE:
2658 case SSE:
2668 // SSEUP should always be preceded by SSE, just widen.
2670 assert(Lo == SSE && "Unexpected SSEUp classification.");
2680 // extra bits in an SSE reg.
2710 assert((Hi != SSEUp || Lo == SSE) && "Invalid SSEUp classification.");
2721 assert((Hi == SSE || Hi == Integer || Hi == X87Up) &&
2764 // AMD64-ABI 3.2.3p3: Rule 3. If the class is SSE, the next
2765 // available SSE register is used, the registers are taken in the
2767 case SSE: {
2799 case SSE:
2808 // eightbyte is passed in the upper half of the last used SSE
2811 assert(Lo == SSE && "Unexpected SSEUp classification");
3186 // SSE registers are spaced 16 bytes apart in the register save
3191 // all the SSE registers to the RSA.
3404 // We can use up to 4 SSE return registers with vectorcall.
3407 // RegCall gives us 16 SSE registers.
3416 // We can use up to 6 SSE register parameters with vectorcall.
3419 // RegCall gives us 16 SSE registers, we can reuse the return registers.