Lines Matching defs:IsSignaling
15233 bool IsSignaling) {
15236 if (IsSignaling)
17128 return getVectorFCmpIR(CmpInst::FCMP_OEQ, /*IsSignaling*/false);
17131 return getVectorFCmpIR(CmpInst::FCMP_OLT, /*IsSignaling*/true);
17134 return getVectorFCmpIR(CmpInst::FCMP_OLE, /*IsSignaling*/true);
17137 return getVectorFCmpIR(CmpInst::FCMP_UNO, /*IsSignaling*/false);
17140 return getVectorFCmpIR(CmpInst::FCMP_UNE, /*IsSignaling*/false);
17143 return getVectorFCmpIR(CmpInst::FCMP_UGE, /*IsSignaling*/true);
17146 return getVectorFCmpIR(CmpInst::FCMP_UGT, /*IsSignaling*/true);
17149 return getVectorFCmpIR(CmpInst::FCMP_ORD, /*IsSignaling*/false);
17184 bool IsSignaling;
17188 case 0x00: Pred = FCmpInst::FCMP_OEQ; IsSignaling = false; break;
17189 case 0x01: Pred = FCmpInst::FCMP_OLT; IsSignaling = true; break;
17190 case 0x02: Pred = FCmpInst::FCMP_OLE; IsSignaling = true; break;
17191 case 0x03: Pred = FCmpInst::FCMP_UNO; IsSignaling = false; break;
17192 case 0x04: Pred = FCmpInst::FCMP_UNE; IsSignaling = false; break;
17193 case 0x05: Pred = FCmpInst::FCMP_UGE; IsSignaling = true; break;
17194 case 0x06: Pred = FCmpInst::FCMP_UGT; IsSignaling = true; break;
17195 case 0x07: Pred = FCmpInst::FCMP_ORD; IsSignaling = false; break;
17196 case 0x08: Pred = FCmpInst::FCMP_UEQ; IsSignaling = false; break;
17197 case 0x09: Pred = FCmpInst::FCMP_ULT; IsSignaling = true; break;
17198 case 0x0a: Pred = FCmpInst::FCMP_ULE; IsSignaling = true; break;
17199 case 0x0b: Pred = FCmpInst::FCMP_FALSE; IsSignaling = false; break;
17200 case 0x0c: Pred = FCmpInst::FCMP_ONE; IsSignaling = false; break;
17201 case 0x0d: Pred = FCmpInst::FCMP_OGE; IsSignaling = true; break;
17202 case 0x0e: Pred = FCmpInst::FCMP_OGT; IsSignaling = true; break;
17203 case 0x0f: Pred = FCmpInst::FCMP_TRUE; IsSignaling = false; break;
17209 IsSignaling = !IsSignaling;
17286 if (IsSignaling)
17293 return getVectorFCmpIR(Pred, IsSignaling);