Lines Matching refs:getOpcode

154     switch (Inst.getOpcode()) {
187     return Inst.getOpcode() == AArch64::ADRP;
191     return Inst.getOpcode() == AArch64::ADR;
195     return Inst.getOpcode() == AArch64::ADDXri;
208     return (Inst.getOpcode() == AArch64::TBNZW ||
209             Inst.getOpcode() == AArch64::TBNZX ||
210             Inst.getOpcode() == AArch64::TBZW ||
211             Inst.getOpcode() == AArch64::TBZX);
215     return (Inst.getOpcode() == AArch64::CBNZW ||
216             Inst.getOpcode() == AArch64::CBNZX ||
217             Inst.getOpcode() == AArch64::CBZW ||
218             Inst.getOpcode() == AArch64::CBZX);
222     return (Inst.getOpcode() == AArch64::MOVKWi ||
223             Inst.getOpcode() == AArch64::MOVKXi ||
224             Inst.getOpcode() == AArch64::MOVNWi ||
225             Inst.getOpcode() == AArch64::MOVNXi ||
226             Inst.getOpcode() == AArch64::MOVZXi ||
227             Inst.getOpcode() == AArch64::MOVZWi);
231     return (Inst.getOpcode() == AArch64::ADDSWri ||
232             Inst.getOpcode() == AArch64::ADDSWrr ||
233             Inst.getOpcode() == AArch64::ADDSWrs ||
234             Inst.getOpcode() == AArch64::ADDSWrx ||
235             Inst.getOpcode() == AArch64::ADDSXri ||
236             Inst.getOpcode() == AArch64::ADDSXrr ||
237             Inst.getOpcode() == AArch64::ADDSXrs ||
238             Inst.getOpcode() == AArch64::ADDSXrx ||
239             Inst.getOpcode() == AArch64::ADDSXrx64 ||
240             Inst.getOpcode() == AArch64::ADDWri ||
241             Inst.getOpcode() == AArch64::ADDWrr ||
242             Inst.getOpcode() == AArch64::ADDWrs ||
243             Inst.getOpcode() == AArch64::ADDWrx ||
244             Inst.getOpcode() == AArch64::ADDXri ||
245             Inst.getOpcode() == AArch64::ADDXrr ||
246             Inst.getOpcode() == AArch64::ADDXrs ||
247             Inst.getOpcode() == AArch64::ADDXrx ||
248             Inst.getOpcode() == AArch64::ADDXrx64);
252     const unsigned opcode = Inst.getOpcode();
290     const unsigned opcode = Inst.getOpcode();
328     const unsigned opcode = Inst.getOpcode();
362     const unsigned opcode = Inst.getOpcode();
385     const unsigned opcode = Inst.getOpcode();
407     const unsigned opcode = Inst.getOpcode();
429     const unsigned opcode = Inst.getOpcode();
456     return (Inst.getOpcode() == AArch64::LDXPX ||
457             Inst.getOpcode() == AArch64::LDXPW ||
458             Inst.getOpcode() == AArch64::LDXRX ||
459             Inst.getOpcode() == AArch64::LDXRW ||
460             Inst.getOpcode() == AArch64::LDXRH ||
461             Inst.getOpcode() == AArch64::LDXRB ||
462             Inst.getOpcode() == AArch64::LDAXPX ||
463             Inst.getOpcode() == AArch64::LDAXPW ||
464             Inst.getOpcode() == AArch64::LDAXRX ||
465             Inst.getOpcode() == AArch64::LDAXRW ||
466             Inst.getOpcode() == AArch64::LDAXRH ||
467             Inst.getOpcode() == AArch64::LDAXRB);
471     return (Inst.getOpcode() == AArch64::STXPX ||
472             Inst.getOpcode() == AArch64::STXPW ||
473             Inst.getOpcode() == AArch64::STXRX ||
474             Inst.getOpcode() == AArch64::STXRW ||
475             Inst.getOpcode() == AArch64::STXRH ||
476             Inst.getOpcode() == AArch64::STXRB ||
477             Inst.getOpcode() == AArch64::STLXPX ||
478             Inst.getOpcode() == AArch64::STLXPW ||
479             Inst.getOpcode() == AArch64::STLXRX ||
480             Inst.getOpcode() == AArch64::STLXRW ||
481             Inst.getOpcode() == AArch64::STLXRH ||
482             Inst.getOpcode() == AArch64::STLXRB);
486     return (Inst.getOpcode() == AArch64::CLREX);
504     if (Inst.getOpcode() == AArch64::FMOVDXr) {
510     if (Inst.getOpcode() != AArch64::ORRXrs)
522     return Inst.getOpcode() == AArch64::BLR;
570     const MCInstrDesc &MCII = Info->get(Inst.getOpcode());
590     if (Inst.getOpcode() == AArch64::ADR) {
604     const MCInstrDesc &MCII = Info->get(Inst.getOpcode());
635     if (Inst.getOpcode() == AArch64::ADRP)
649     const MCInstrDesc &MCII = Info->get(Inst.getOpcode());
778     if (BinExpr && BinExpr->getOpcode() == MCBinaryExpr::Add)
845     assert(Inst.getOpcode() == AArch64::BR && "Unexpected opcode");
862     if (DefAdd->getOpcode() == AArch64::ADDXri) {
870     if (DefAdd->getOpcode() == AArch64::ADDXrs) {
886     if (DefAdd->getOpcode() != AArch64::ADDXrx)
927     if (DefBaseAddr->getOpcode() != AArch64::ADR)
948     if (DefJTBaseAdd->getOpcode() == AArch64::ADR) {
961     if (DefJTBaseAdd->getOpcode() != AArch64::ADDXri) {
974     if (DefJTBasePage->getOpcode() != AArch64::ADRP)
1101     assert(Branch->getOpcode() == AArch64::BR && "Unexpected opcode");
1113     if (Ldr->getOpcode() != AArch64::LDRXui)
1128     if (Adrp->getOpcode() != AArch64::ADRP)
1169     return Inst.getOpcode();
1186       Inst.setOpcode(getInvertedBranchOpcode(Inst.getOpcode()));
1187       assert(Inst.getOpcode() != 0 && "Invalid branch instruction");
1188     } else if (Inst.getOpcode() == AArch64::Bcc) {
1202     switch (Inst.getOpcode()) {
1273     assert((DirectCall.getOpcode() == AArch64::BL ||
1274             (DirectCall.getOpcode() == AArch64::B && IsTailCall)) &&
1317     return Inst.getOpcode() == AArch64::HINT &&
1328     const unsigned opcode = Inst.getOpcode();
1385     const unsigned opcode = Inst.getOpcode();
1680     if (CurInst.getOpcode() != AArch64::BR || !CurInst.getOperand(0).isReg() ||
1690     if (I == Begin || I->getOpcode() != AArch64::ADDXri ||
1701     if (I->getOpcode() != AArch64::ADRP ||
1733     if (LDRInst.getOpcode() != AArch64::LDRXl)
1745     if (BRInst.getOpcode() != AArch64::BR)
1959     if (Inst.getOpcode() == AArch64::BR || Inst.getOpcode() == AArch64::BLR) {