Lines Matching full:pi
149 struct pci_io pi;
155 bzero(&pi, sizeof(pi));
156 pi.pi_sel = *sel;
157 pi.pi_reg = reg;
158 pi.pi_width = width;
160 if (ioctl(pcifd, PCIOCREAD, &pi) < 0)
163 return (pi.pi_data);
170 struct pci_io pi;
176 bzero(&pi, sizeof(pi));
177 pi.pi_sel = *sel;
178 pi.pi_reg = reg;
179 pi.pi_width = width;
180 pi.pi_data = data;
182 (void)ioctl(pcifd, PCIOCWRITE, &pi); /* XXX */
187 passthru_add_msicap(struct pci_devinst *pi, int msgnum, int nextptr)
204 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
216 struct pci_devinst *pi;
220 pi = sc->psc_pi;
246 pci_set_cfgdata32(pi, capptr, u32);
262 pci_set_cfgdata32(pi, capptr, u32);
274 pi->pi_msix.pba_bar =
276 pi->pi_msix.pba_offset =
278 pi->pi_msix.table_bar =
280 pi->pi_msix.table_offset =
282 pi->pi_msix.table_count = MSIX_TABLE_COUNT(msixcap.msgctrl);
283 pi->pi_msix.pba_size = PBA_SIZE(pi->pi_msix.table_count);
286 table_size = pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
287 pi->pi_msix.table = calloc(1, table_size);
290 for (i = 0; i < pi->pi_msix.table_count; i++) {
291 pi->pi_msix.table[i].vector_control |=
305 msiptr = passthru_add_msicap(pi, 1, origptr);
307 sc->psc_msi.msgctrl = pci_get_cfgdata16(pi, msiptr + 2);
309 pci_set_cfgdata8(pi, PCIR_CAP_PTR, msiptr);
323 struct pci_devinst *pi;
334 pi = sc->psc_pi;
336 table_offset = pi->pi_msix.table_offset;
337 table_count = pi->pi_msix.table_count;
342 src8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
346 src16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
350 src32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
354 src64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
367 entry = &pi->pi_msix.table[index];
398 struct pci_devinst *pi;
408 pi = sc->psc_pi;
410 table_offset = pi->pi_msix.table_offset;
411 table_count = pi->pi_msix.table_count;
416 dest8 = (uint8_t *)(pi->pi_msix.mapped_addr + offset);
420 dest16 = (uint16_t *)(pi->pi_msix.mapped_addr + offset);
424 dest32 = (uint32_t *)(pi->pi_msix.mapped_addr + offset);
428 dest64 = (uint64_t *)(pi->pi_msix.mapped_addr + offset);
439 entry = &pi->pi_msix.table[index];
450 if (pi->pi_msix.enabled) {
465 struct pci_devinst *pi = sc->psc_pi;
470 assert(pci_msix_table_bar(pi) >= 0 && pci_msix_pba_bar(pi) >= 0);
487 pbm.pbm_reg = PCIR_BAR(pi->pi_msix.table_bar);
495 pi->pi_msix.mapped_addr = (uint8_t *)(uintptr_t)pbm.pbm_map_base;
496 pi->pi_msix.mapped_size = pbm.pbm_map_length;
498 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
500 table_size = pi->pi_msix.table_offset - table_offset;
501 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
510 if (mprotect(pi->pi_msix.mapped_addr, table_offset,
513 if (table_offset + table_size != pi->pi_msix.mapped_size)
515 pi->pi_msix.mapped_addr + table_offset + table_size,
516 pi->pi_msix.mapped_size - (table_offset + table_size),
527 struct pci_devinst *pi;
532 pi = sc->psc_pi;
578 error = pci_emul_alloc_bar(pi, i, bartype, size);
591 pi->pi_bar[i].lobits = lobits;
606 cfginit(struct pci_devinst *pi, int bus, int slot, int func)
614 sc = pi->pi_arg;
626 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
627 intline = pci_get_cfgdata8(pi, PCIR_INTLINE);
628 intpin = pci_get_cfgdata8(pi, PCIR_INTPIN);
630 pci_set_cfgdata32(pi, i,
633 pci_set_cfgdata16(pi, PCIR_COMMAND, cmd);
634 pci_set_cfgdata8(pi, PCIR_INTLINE, intline);
635 pci_set_cfgdata8(pi, PCIR_INTPIN, intpin);
649 if (pci_msix_table_bar(pi) >= 0) {
853 passthru_init(struct pci_devinst *pi, nvlist_t *nvl)
864 memflags = vm_get_memflags(pi->pi_vmctx);
893 if (vm_assign_pptdev(pi->pi_vmctx, bus, slot, func) != 0) {
901 pi->pi_arg = sc;
902 sc->psc_pi = pi;
905 if ((error = cfginit(pi, bus, slot, func)) != 0)
925 if (devp->probe(pi) == 0) {
932 error = dev->init(pi, nvl);
941 dev->deinit(pi);
943 vm_unassign_pptdev(pi->pi_vmctx, bus, slot, func);
976 struct pci_devinst *pi __unused, int coff, int bytes, uint32_t *rv)
993 pci_get_cfgdata16(pi, PCIR_COMMAND);
1005 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused,
1012 passthru_cfgread(struct pci_devinst *pi, int coff, int bytes, uint32_t *rv)
1016 sc = pi->pi_arg;
1019 return (sc->psc_pcir_rhandler[coff](sc, pi, coff, bytes, rv));
1021 return (passthru_cfgread_default(sc, pi, coff, bytes, rv));
1025 passthru_cfgwrite_default(struct passthru_softc *sc, struct pci_devinst *pi,
1035 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff,
1037 error = vm_setup_pptdev_msi(pi->pi_vmctx, sc->psc_sel.pc_bus,
1039 pi->pi_msi.addr, pi->pi_msi.msg_data,
1040 pi->pi_msi.maxmsgnum);
1047 pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msix.capoff,
1049 if (pi->pi_msix.enabled) {
1050 msix_table_entries = pi->pi_msix.table_count;
1052 error = vm_setup_pptdev_msix(pi->pi_vmctx,
1055 pi->pi_msix.table[i].addr,
1056 pi->pi_msix.table[i].msg_data,
1057 pi->pi_msix.table[i].vector_control);
1063 error = vm_disable_pptdev_msix(pi->pi_vmctx,
1084 cmd_old = pci_get_cfgdata16(pi, PCIR_COMMAND);
1085 pci_set_cfgdata16(pi, PCIR_COMMAND, val & 0xffff);
1086 pci_emul_cmd_changed(pi, cmd_old);
1097 struct pci_devinst *pi __unused, int coff __unused, int bytes __unused,
1104 passthru_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val)
1108 sc = pi->pi_arg;
1111 return (sc->psc_pcir_whandler[coff](sc, pi, coff, bytes, val));
1113 return (passthru_cfgwrite_default(sc, pi, coff, bytes, val));
1117 passthru_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
1123 sc = pi->pi_arg;
1125 if (baridx == pci_msix_table_bar(pi)) {
1128 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
1145 passthru_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
1151 sc = pi->pi_arg;
1153 if (baridx == pci_msix_table_bar(pi)) {
1156 assert(pi->pi_bar[baridx].type == PCIBAR_IO);
1176 passthru_msix_addr(struct pci_devinst *pi, int baridx, int enabled,
1183 sc = pi->pi_arg;
1184 table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
1187 if (vm_unmap_pptdev_mmio(pi->pi_vmctx,
1194 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1202 table_size = pi->pi_msix.table_offset - table_offset;
1203 table_size += pi->pi_msix.table_count * MSIX_TABLE_ENTRY_SIZE;
1205 remaining = pi->pi_bar[baridx].size - table_offset - table_size;
1209 if (vm_unmap_pptdev_mmio(pi->pi_vmctx,
1216 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1228 passthru_mmio_addr(struct pci_devinst *pi, int baridx, int enabled,
1233 sc = pi->pi_arg;
1235 if (vm_unmap_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1241 if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
1251 passthru_addr_rom(struct pci_devinst *const pi, const int idx,
1254 const uint64_t addr = pi->pi_bar[idx].addr;
1255 const uint64_t size = pi->pi_bar[idx].size;
1258 if (vm_munmap_memseg(pi->pi_vmctx, addr, size) != 0) {
1264 if (vm_mmap_memseg(pi->pi_vmctx, addr, VM_PCIROM,
1265 pi->pi_romoffset, size, PROT_READ | PROT_EXEC) != 0) {
1273 passthru_addr(struct pci_devinst *pi, int baridx, int enabled, uint64_t address)
1275 switch (pi->pi_bar[baridx].type) {
1280 passthru_addr_rom(pi, baridx, enabled);
1284 if (baridx == pci_msix_table_bar(pi))
1285 passthru_msix_addr(pi, baridx, enabled, address);
1287 passthru_mmio_addr(pi, baridx, enabled, address);
1291 pi->pi_bar[baridx].type);