Lines Matching full:pi
158 static void pci_lintr_route(struct pci_devinst *pi);
159 static void pci_lintr_update(struct pci_devinst *pi);
166 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
170 pci_set_cfgdata8(pi, coff, val);
172 pci_set_cfgdata16(pi, coff, val);
174 pci_set_cfgdata32(pi, coff, val);
178 CFGREAD(struct pci_devinst *pi, int coff, int bytes)
182 return (pci_get_cfgdata8(pi, coff));
184 return (pci_get_cfgdata16(pi, coff));
186 return (pci_get_cfgdata32(pi, coff));
402 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset)
405 if (offset < pi->pi_msix.pba_offset)
408 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) {
416 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
431 if (tab_index >= pi->pi_msix.table_count)
440 dest = (char *)(pi->pi_msix.table + tab_index);
452 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size)
476 if (tab_index < pi->pi_msix.table_count) {
478 dest = (char *)(pi->pi_msix.table + tab_index);
487 } else if (pci_valid_pba_offset(pi, offset)) {
496 pci_msix_table_bar(struct pci_devinst *pi)
499 if (pi->pi_msix.table != NULL)
500 return (pi->pi_msix.table_bar);
506 pci_msix_pba_bar(struct pci_devinst *pi)
509 if (pi->pi_msix.table != NULL)
510 return (pi->pi_msix.pba_bar);
636 modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
642 pe = pi->pi_d;
643 type = pi->pi_bar[idx].type;
651 iop.name = pi->pi_name;
652 iop.port = pi->pi_bar[idx].addr;
653 iop.size = pi->pi_bar[idx].size;
657 iop.arg = pi;
665 mr.name = pi->pi_name;
666 mr.base = pi->pi_bar[idx].addr;
667 mr.size = pi->pi_bar[idx].size;
671 mr.arg1 = pi;
685 mr.name = pi->pi_name;
686 mr.base = pi->pi_bar[idx].addr;
687 mr.size = pi->pi_bar[idx].size;
691 mr.arg1 = pi;
708 (*pe->pe_baraddr)(pi, idx, registration, pi->pi_bar[idx].addr);
712 unregister_bar(struct pci_devinst *pi, int idx)
715 modify_bar_registration(pi, idx, 0);
719 register_bar(struct pci_devinst *pi, int idx)
722 modify_bar_registration(pi, idx, 1);
727 romen(struct pci_devinst *pi)
729 return (pi->pi_bar[PCI_ROM_IDX].lobits & PCIM_BIOS_ENABLE) ==
735 porten(struct pci_devinst *pi)
739 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
746 memen(struct pci_devinst *pi)
750 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
762 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type)
766 if (pi->pi_bar[idx].type == PCIBAR_IO)
767 decode = porten(pi);
769 decode = memen(pi);
772 unregister_bar(pi, idx);
777 pi->pi_bar[idx].addr = addr;
780 pi->pi_bar[idx].addr &= ~0xffffffffUL;
781 pi->pi_bar[idx].addr |= addr;
784 pi->pi_bar[idx].addr &= 0xffffffff;
785 pi->pi_bar[idx].addr |= addr;
792 register_bar(pi, idx);
1045 pci_emul_add_boot_device(struct pci_devinst *pi, int bootindex)
1051 errx(4, "Invalid bootindex %d for %s", bootindex, pi->pi_name);
1059 new_device->pdi = pi;
1067 bootindex, pi->pi_name, device->pdi->pi_name);
1085 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen)
1094 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1098 capoff = pi->pi_capend + 1;
1106 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff);
1107 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT);
1109 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff);
1113 pci_set_cfgdata8(pi, capoff + i, capdata[i]);
1116 pci_set_cfgdata8(pi, capoff + 1, 0);
1118 pi->pi_prevcap = capoff;
1119 pi->pi_capend = capoff + reallen - 1;
1191 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum)
1197 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap)));
1227 pci_msix_table_init(struct pci_devinst *pi, int table_entries)
1235 pi->pi_msix.table = calloc(1, table_size);
1239 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK;
1243 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum)
1256 pi->pi_msix.table_bar = barnum;
1257 pi->pi_msix.pba_bar = barnum;
1258 pi->pi_msix.table_offset = 0;
1259 pi->pi_msix.table_count = msgnum;
1260 pi->pi_msix.pba_offset = tab_size;
1261 pi->pi_msix.pba_size = PBA_SIZE(msgnum);
1263 pci_msix_table_init(pi, msgnum);
1268 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32,
1269 tab_size + pi->pi_msix.pba_size);
1271 return (pci_emul_add_capability(pi, (u_char *)&msixcap,
1276 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1286 msgctrl = pci_get_cfgdata16(pi, offset);
1291 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
1292 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
1293 pci_lintr_update(pi);
1296 CFGWRITE(pi, offset, val, bytes);
1300 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
1312 msgctrl = pci_get_cfgdata16(pi, offset);
1317 CFGWRITE(pi, offset, val, bytes);
1319 msgctrl = pci_get_cfgdata16(pi, capoff + 2);
1320 addrlo = pci_get_cfgdata32(pi, capoff + 4);
1322 msgdata = pci_get_cfgdata16(pi, capoff + 12);
1324 msgdata = pci_get_cfgdata16(pi, capoff + 8);
1327 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0;
1328 if (pi->pi_msi.enabled) {
1329 pi->pi_msi.addr = addrlo;
1330 pi->pi_msi.msg_data = msgdata;
1331 pi->pi_msi.maxmsgnum = 1 << (mme >> 4);
1333 pi->pi_msi.maxmsgnum = 0;
1335 pci_lintr_update(pi);
1339 pciecap_cfgwrite(struct pci_devinst *pi, int capoff __unused, int offset,
1344 CFGWRITE(pi, offset, val, bytes);
1349 pci_emul_add_pciecap(struct pci_devinst *pi, int type)
1362 if ((type == PCIEM_TYPE_ENDPOINT) && (pi->pi_bus == 0))
1372 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap));
1382 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val,
1395 nextoff = pci_get_cfgdata8(pi, capoff + 1);
1404 capid = pci_get_cfgdata8(pi, capoff);
1424 msicap_cfgwrite(pi, capoff, offset, bytes, val);
1427 msixcap_cfgwrite(pi, capoff, offset, bytes, val);
1430 pciecap_cfgwrite(pi, capoff, offset, bytes, val);
1438 pci_emul_iscap(struct pci_devinst *pi, int offset)
1442 sts = pci_get_cfgdata16(pi, PCIR_STATUS);
1444 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend)
1750 struct pci_devinst *pi;
1886 pi = si->si_funcs[func].fi_devi;
1887 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
1888 pi->pi_d->pe_write_dsdt(pi);
1926 pci_msi_enabled(struct pci_devinst *pi)
1928 return (pi->pi_msi.enabled);
1932 pci_msi_maxmsgnum(struct pci_devinst *pi)
1934 if (pi->pi_msi.enabled)
1935 return (pi->pi_msi.maxmsgnum);
1941 pci_msix_enabled(struct pci_devinst *pi)
1944 return (pi->pi_msix.enabled && !pi->pi_msi.enabled);
1948 pci_generate_msix(struct pci_devinst *pi, int index)
1952 if (!pci_msix_enabled(pi))
1955 if (pi->pi_msix.function_mask)
1958 if (index >= pi->pi_msix.table_count)
1961 mte = &pi->pi_msix.table[index];
1964 vm_raise_msi(pi->pi_vmctx, mte->addr, mte->msg_data,
1965 pi->pi_bus, pi->pi_slot, pi->pi_func);
1970 pci_generate_msi(struct pci_devinst *pi, int index)
1973 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) {
1974 vm_raise_msi(pi->pi_vmctx, pi->pi_msi.addr,
1975 pi->pi_msi.msg_data + index,
1976 pi->pi_bus, pi->pi_slot, pi->pi_func);
1981 pci_lintr_permitted(struct pci_devinst *pi)
1985 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
1986 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
1991 pci_lintr_request(struct pci_devinst *pi)
1997 bi = pci_businfo[pi->pi_bus];
2004 si = &bi->slotinfo[pi->pi_slot];
2015 pi->pi_lintr.pin = bestpin + 1;
2016 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
2020 pci_lintr_route(struct pci_devinst *pi)
2026 if (pi->pi_lintr.pin == 0)
2029 bi = pci_businfo[pi->pi_bus];
2031 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1];
2033 pci_irq_route(pi, irq);
2034 pi->pi_lintr.irq = *irq;
2035 pci_set_cfgdata8(pi, PCIR_INTLINE, pci_irq_intline(irq));
2039 pci_lintr_assert(struct pci_devinst *pi)
2042 assert(pi->pi_lintr.pin > 0);
2044 pthread_mutex_lock(&pi->pi_lintr.lock);
2045 if (pi->pi_lintr.state == IDLE) {
2046 if (pci_lintr_permitted(pi)) {
2047 pi->pi_lintr.state = ASSERTED;
2048 pci_irq_assert(pi);
2050 pi->pi_lintr.state = PENDING;
2052 pthread_mutex_unlock(&pi->pi_lintr.lock);
2056 pci_lintr_deassert(struct pci_devinst *pi)
2059 assert(pi->pi_lintr.pin > 0);
2061 pthread_mutex_lock(&pi->pi_lintr.lock);
2062 if (pi->pi_lintr.state == ASSERTED) {
2063 pi->pi_lintr.state = IDLE;
2064 pci_irq_deassert(pi);
2065 } else if (pi->pi_lintr.state == PENDING)
2066 pi->pi_lintr.state = IDLE;
2067 pthread_mutex_unlock(&pi->pi_lintr.lock);
2071 pci_lintr_update(struct pci_devinst *pi)
2074 pthread_mutex_lock(&pi->pi_lintr.lock);
2075 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
2076 pci_irq_deassert(pi);
2077 pi->pi_lintr.state = PENDING;
2078 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
2079 pi->pi_lintr.state = ASSERTED;
2080 pci_irq_assert(pi);
2082 pthread_mutex_unlock(&pi->pi_lintr.lock);
2182 pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old)
2187 new = pci_get_cfgdata16(pi, PCIR_COMMAND);
2195 switch (pi->pi_bar[i].type) {
2203 register_bar(pi, i);
2205 unregister_bar(pi, i);
2210 if (!romen(pi))
2218 register_bar(pi, i);
2220 unregister_bar(pi, i);
2232 pci_lintr_update(pi);
2236 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
2241 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */
2253 old = CFGREAD(pi, coff, bytes);
2256 CFGWRITE(pi, coff, new, bytes); /* update config */
2258 pci_emul_cmd_changed(pi, cmd);
2267 struct pci_devinst *pi;
2274 pi = si->si_funcs[func].fi_devi;
2276 pi = NULL;
2282 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
2308 pe = pi->pi_d;
2316 needcfg = pe->pe_cfgread(pi, coff, bytes, valp);
2322 *valp = CFGREAD(pi, coff, bytes);
2328 (*pe->pe_cfgwrite)(pi, coff, bytes, *valp) == 0)
2351 mask = ~(pi->pi_bar[idx].size - 1);
2352 switch (pi->pi_bar[idx].type) {
2354 pi->pi_bar[idx].addr = bar = 0;
2361 bar = addr | pi->pi_bar[idx].lobits;
2365 if (addr != pi->pi_bar[idx].addr) {
2366 update_bar_address(pi, addr, idx,
2372 bar |= pi->pi_bar[idx].lobits;
2373 if (addr != pi->pi_bar[idx].addr) {
2374 update_bar_address(pi, addr, idx,
2380 bar |= pi->pi_bar[idx].lobits;
2381 if (addr != (uint32_t)pi->pi_bar[idx].addr) {
2382 update_bar_address(pi, addr, idx,
2387 mask = ~(pi->pi_bar[idx - 1].size - 1);
2390 if (bar != pi->pi_bar[idx - 1].addr >> 32) {
2391 update_bar_address(pi, addr, idx - 1,
2397 if (memen(pi) && romen(pi)) {
2398 unregister_bar(pi, idx);
2400 pi->pi_bar[idx].addr = addr;
2401 pi->pi_bar[idx].lobits = *valp &
2404 if (memen(pi) && romen(pi)) {
2405 register_bar(pi, idx);
2407 bar |= pi->pi_bar[idx].lobits;
2412 pci_set_cfgdata32(pi, coff, bar);
2414 } else if (pci_emul_iscap(pi, coff)) {
2415 pci_emul_capwrite(pi, coff, bytes, *valp, 0, 0);
2417 pci_emul_cmdsts_write(pi, coff, *valp, bytes);
2419 CFGWRITE(pi, coff, *valp, bytes);
2489 struct pci_devinst *pi;
2493 pi = meta->dev_data;
2495 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.enabled, meta, ret, done);
2496 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.addr, meta, ret, done);
2497 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.msg_data, meta, ret, done);
2498 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msi.maxmsgnum, meta, ret, done);
2500 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.enabled, meta, ret, done);
2501 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_bar, meta, ret, done);
2502 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_bar, meta, ret, done);
2503 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_offset, meta, ret, done);
2504 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table_count, meta, ret, done);
2505 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_offset, meta, ret, done);
2506 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.pba_size, meta, ret, done);
2507 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.function_mask, meta, ret, done);
2509 SNAPSHOT_BUF_OR_LEAVE(pi->pi_cfgdata, sizeof(pi->pi_cfgdata),
2512 for (i = 0; i < (int)nitems(pi->pi_bar); i++) {
2513 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].type, meta, ret, done);
2514 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].size, meta, ret, done);
2515 SNAPSHOT_VAR_OR_LEAVE(pi->pi_bar[i].addr, meta, ret, done);
2519 for (i = 0; i < pi->pi_msix.table_count; i++) {
2520 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].addr,
2522 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].msg_data,
2524 SNAPSHOT_VAR_OR_LEAVE(pi->pi_msix.table[i].vector_control,
2597 pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused)
2604 pi->pi_arg = sc;
2606 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001);
2607 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD);
2608 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02);
2610 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS);
2613 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ);
2616 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ);
2619 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ);
2626 pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
2630 struct pci_emul_dsoftc *sc = pi->pi_arg;
2652 if (offset == 4 && size == 4 && pci_msi_enabled(pi))
2653 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi));
2656 for (i = 0; i < pci_msi_maxmsgnum(pi); i++)
2657 pci_generate_msi(pi, i);
2693 pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
2695 struct pci_emul_dsoftc *sc = pi->pi_arg;