Lines Matching full:unit
111 dmar_pglvl_supported(struct dmar_unit *unit, int pglvl)
118 if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
153 dmar_maxaddr2mgaw(struct dmar_unit *unit, iommu_gaddr_t maxaddr, bool allow_less)
159 (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0)
165 } while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap)
203 calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size,
209 for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) {
224 dmar_flush_transl_to_ram(struct dmar_unit *unit, void *dst, size_t sz)
227 if (DMAR_IS_COHERENT(unit))
237 dmar_flush_pte_to_ram(struct dmar_unit *unit, iommu_pte_t *dst)
240 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
244 dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst)
247 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
251 dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst)
254 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst));
262 dmar_load_root_entry_ptr(struct dmar_unit *unit)
271 DMAR_ASSERT_LOCKED(unit);
273 VM_OBJECT_RLOCK(unit->ctx_obj);
274 root_entry = vm_page_lookup(unit->ctx_obj, 0);
275 VM_OBJECT_RUNLOCK(unit->ctx_obj);
276 dmar_write8(unit, DMAR_RTADDR_REG, VM_PAGE_TO_PHYS(root_entry));
277 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SRTP);
278 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_RTPS)
288 dmar_inv_ctx_glob(struct dmar_unit *unit)
296 DMAR_ASSERT_LOCKED(unit);
297 KASSERT(!unit->qi_enabled, ("QI enabled"));
305 dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB);
306 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32)
315 dmar_inv_iotlb_glob(struct dmar_unit *unit)
319 DMAR_ASSERT_LOCKED(unit);
320 KASSERT(!unit->qi_enabled, ("QI enabled"));
322 reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap);
324 dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT |
326 DMAR_WAIT_UNTIL(((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) &
336 dmar_flush_write_bufs(struct dmar_unit *unit)
340 DMAR_ASSERT_LOCKED(unit);
345 KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0,
346 ("dmar%d: no RWBF", unit->iommu.unit));
348 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF);
349 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS)
361 dmar_disable_protected_regions(struct dmar_unit *unit)
366 DMAR_ASSERT_LOCKED(unit);
369 if ((unit->hw_cap & (DMAR_CAP_PLMR | DMAR_CAP_PHMR)) == 0)
372 reg = dmar_read4(unit, DMAR_PMEN_REG);
377 dmar_write4(unit, DMAR_PMEN_REG, reg);
378 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_PMEN_REG) & DMAR_PMEN_PRS)
385 dmar_enable_translation(struct dmar_unit *unit)
389 DMAR_ASSERT_LOCKED(unit);
390 unit->hw_gcmd |= DMAR_GCMD_TE;
391 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
392 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES)
398 dmar_disable_translation(struct dmar_unit *unit)
402 DMAR_ASSERT_LOCKED(unit);
403 unit->hw_gcmd &= ~DMAR_GCMD_TE;
404 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
405 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES)
411 dmar_load_irt_ptr(struct dmar_unit *unit)
416 DMAR_ASSERT_LOCKED(unit);
417 irta = unit->irt_phys;
418 if (DMAR_X2APIC(unit))
420 s = fls(unit->irte_cnt) - 2;
421 KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK &&
422 powerof2(unit->irte_cnt),
423 ("IRTA_REG_S overflow %x", unit->irte_cnt));
425 dmar_write8(unit, DMAR_IRTA_REG, irta);
426 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP);
427 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS)
433 dmar_enable_ir(struct dmar_unit *unit)
437 DMAR_ASSERT_LOCKED(unit);
438 unit->hw_gcmd |= DMAR_GCMD_IRE;
439 unit->hw_gcmd &= ~DMAR_GCMD_CFI;
440 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
441 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES)
447 dmar_disable_ir(struct dmar_unit *unit)
451 DMAR_ASSERT_LOCKED(unit);
452 unit->hw_gcmd &= ~DMAR_GCMD_IRE;
453 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd);
454 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES)
484 ("dmar%d barrier %d missing done", dmar->iommu.unit,
502 ("dmar%d barrier %d missed entry", dmar->iommu.unit, barrier_id));