Lines Matching +full:low +full:- +full:to +full:- +full:high
1 /*-
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
65 uint64_t low, uint16_t rid);
77 if (unit == NULL || !unit->ir_enabled) {
79 cookies[i] = -1;
83 error = vmem_alloc(unit->irtids, count, M_FIRSTFIT | M_NOWAIT,
101 uint64_t low;
110 * See VT-d specification, 5.1.6 Remapping Hardware -
121 if (unit == NULL || !unit->ir_enabled || cookie == -1)
124 low = (DMAR_X2APIC(unit) ? DMAR_IRTE1_DST_x2APIC(cpu) :
128 dmar_ir_program_irte(unit, cookie, low, rid);
132 * See VT-d specification, 5.1.5.2 MSI and MSI-X
147 if (cookie == -1)
159 uint64_t low, iorte;
165 if (unit == NULL || !unit->ir_enabled) {
166 *cookie = -1;
170 error = vmem_alloc(unit->irtids, 1, M_FIRSTFIT | M_NOWAIT, &vmem_res);
177 low = 0;
180 low |= DMAR_IRTE1_DLM_ExtINT;
183 low |= DMAR_IRTE1_DLM_NMI;
186 low |= DMAR_IRTE1_DLM_SMI;
190 low |= DMAR_IRTE1_DLM_FM | DMAR_IRTE1_V(vector);
193 low |= (DMAR_X2APIC(unit) ? DMAR_IRTE1_DST_x2APIC(cpu) :
197 dmar_ir_program_irte(unit, idx, low, rid);
201 * See VT-d specification, 5.1.5.1 I/OxAPIC
223 if (idx == -1)
225 *cookie = -1;
227 KASSERT(unit != NULL && unit->ir_enabled,
239 * We need to determine if the interrupt source generates FSB
263 dmar_ir_program_irte(struct dmar_unit *unit, u_int idx, uint64_t low,
267 uint64_t high;
269 KASSERT(idx < unit->irte_cnt,
270 ("bad cookie %d %d", idx, unit->irte_cnt));
271 irte = &(unit->irt[idx]);
272 high = DMAR_IRTE2_SVT_RID | DMAR_IRTE2_SQ_RID |
275 device_printf(unit->iommu.dev,
276 "programming irte[%d] rid %#x high %#jx low %#jx\n",
277 idx, rid, (uintmax_t)high, (uintmax_t)low);
280 if ((irte->irte1 & DMAR_IRTE1_P) != 0) {
283 * is to remap the interrupt for balancing. Only low
284 * word of rte needs to be changed. Assert that the
285 * high word contains expected value.
287 KASSERT(irte->irte2 == high,
288 ("irte2 mismatch, %jx %jx", (uintmax_t)irte->irte2,
289 (uintmax_t)high));
290 dmar_pte_update(&irte->irte1, low);
292 dmar_pte_store(&irte->irte2, high);
293 dmar_pte_store(&irte->irte1, low);
305 KASSERT(unit != NULL && unit->ir_enabled,
307 KASSERT(cookie < unit->irte_cnt,
308 ("bad cookie %u %u", cookie, unit->irte_cnt));
309 irte = &(unit->irt[cookie]);
310 dmar_pte_clear(&irte->irte1);
311 dmar_pte_clear(&irte->irte2);
315 vmem_free(unit->irtids, cookie, 1);
322 SYSCTL_ADD_INT(&unit->iommu.sysctl_ctx,
323 SYSCTL_CHILDREN(device_get_sysctl_tree(unit->iommu.dev)),
324 OID_AUTO, "ir", CTLFLAG_RD, &unit->ir_enabled, 0,
326 if ((unit->hw_ecap & DMAR_ECAP_IR) == 0)
328 unit->ir_enabled = 1;
329 TUNABLE_INT_FETCH("hw.dmar.ir", &unit->ir_enabled);
330 TUNABLE_INT_FETCH("hw.iommu.ir", &unit->ir_enabled);
331 if (!unit->ir_enabled)
333 if (!unit->qi_enabled) {
334 unit->ir_enabled = 0;
336 device_printf(unit->iommu.dev,
340 unit->irte_cnt = roundup_pow_of_two(num_io_irqs);
341 if (unit->memdomain == -1) {
342 unit->irt = kmem_alloc_contig(
343 unit->irte_cnt * sizeof(dmar_irte_t),
348 unit->irt = kmem_alloc_contig_domainset(
349 DOMAINSET_PREF(unit->memdomain),
350 unit->irte_cnt * sizeof(dmar_irte_t),
355 if (unit->irt == NULL)
357 unit->irt_phys = pmap_kextract((vm_offset_t)unit->irt);
358 unit->irtids = vmem_create("dmarirt", 0, unit->irte_cnt, 1, 0,
382 unit->ir_enabled = 0;
383 if (unit->irt != NULL) {
386 vmem_destroy(unit->irtids);
387 kmem_free(unit->irt, unit->irte_cnt * sizeof(dmar_irte_t));