Lines Matching defs:dmd
298 struct iommu_msi_data *dmd;
305 dmd = &unit->x86c.intrs[i];
306 if (irq == dmd->irq) {
313 dmd->msi_data = msi_data;
314 dmd->msi_addr = msi_addr;
315 (dmd->disable_intr)(DMAR2IOMMU(unit));
316 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data);
317 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr);
318 dmar_write4(unit, dmd->msi_uaddr_reg,
319 dmd->msi_addr >> 32);
320 (dmd->enable_intr)(DMAR2IOMMU(unit));
364 struct iommu_msi_data *dmd;
400 dmd = &unit->x86c.intrs[DMAR_INTR_FAULT];
401 dmd->name = "fault";
402 dmd->irq_rid = DMAR_FAULT_IRQ_RID;
403 dmd->handler = dmar_fault_intr;
404 dmd->msi_data_reg = DMAR_FEDATA_REG;
405 dmd->msi_addr_reg = DMAR_FEADDR_REG;
406 dmd->msi_uaddr_reg = DMAR_FEUADDR_REG;
407 dmd->enable_intr = dmar_enable_fault_intr;
408 dmd->disable_intr = dmar_disable_fault_intr;
415 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data);
416 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr);
417 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32);
420 dmd = &unit->x86c.intrs[DMAR_INTR_QI];
421 dmd->name = "qi";
422 dmd->irq_rid = DMAR_QI_IRQ_RID;
423 dmd->handler = dmar_qi_intr;
424 dmd->msi_data_reg = DMAR_IEDATA_REG;
425 dmd->msi_addr_reg = DMAR_IEADDR_REG;
426 dmd->msi_uaddr_reg = DMAR_IEUADDR_REG;
427 dmd->enable_intr = dmar_enable_qi_intr;
428 dmd->disable_intr = dmar_disable_qi_intr;
436 dmar_write4(unit, dmd->msi_data_reg, dmd->msi_data);
437 dmar_write4(unit, dmd->msi_addr_reg, dmd->msi_addr);
438 dmar_write4(unit, dmd->msi_uaddr_reg, dmd->msi_addr >> 32);