Lines Matching full:enables
968 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
969 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
970 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
975 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
978 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
979 #define CCR1_SMI 0x02 /* Enables SMM pins */
986 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
994 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
995 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
999 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
1002 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
1003 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
1004 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
1005 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
1009 #define CCR4_MEM 0x08 /* Enables memory bypassing */
1010 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
1012 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
1018 #define CCR5_ARREN 0x20 /* Enables ARR region */
1026 #define PCR0_RSTK 0x01 /* Enables return stack */
1027 #define PCR0_BTB 0x02 /* Enables branch target buffer */
1028 #define PCR0_LOOP 0x04 /* Enables loop */
1029 #define PCR0_AIS 0x08 /* Enables all instructions stalled to
1031 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
1032 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
1195 #define RCR_RCE 0x01 /* Enables caching for ARR7. */