17 	Op_A    =	0x00000001,
18 	Op_B    =	0x00000002,
19 	Op_BI   =	0x00000004,
20 	Op_BO   =	0x00000008,
22 	Op_CRM  =	0x00000010,
23 	Op_D    =	0x00000020,
24 	Op_ST   =	0x00000020,  /* Op_S for store-operations, same as D */
25 	Op_S    =	0x00000040,  /* S-field is swapped with A-field */
27 	Op_dA  =	0x00000080,
28 	Op_LK   =	0x00000100,
29 	Op_Rc   =	0x00000200,
33 	Op_OE   =	0x00000400,
34 	Op_SR   =	0x00000800,
35 	Op_TO   =	0x00001000,
36 	Op_sign =	0x00002000,
37 	Op_const =	0x00004000,
40 	Op_crbA =	0x00008000,
41 	Op_crbB =	0x00010000,
44 	Op_crbD =	0x00020000,
45 	Op_crfD =	0x00040000,
46 	Op_crfS =	0x00080000,
47 	Op_ds   =	0x00100000,
48 	Op_me   =	0x00200000,
49 	Op_spr  =	0x00400000,
51 	Op_tbr  =	0x00800000,
53 	Op_BP	=	0x01000000,
54 	Op_BD	=	0x02000000,
55 	Op_LI	=	0x04000000,
56 	Op_C	=	0x08000000,
58 	Op_NB	=	0x10000000,
60 	Op_sh_mb_sh =	0x20000000,
61 	Op_sh   =	0x40000000,
63 	Op_mb	=	0x80000000,
116 	{ "tdi",	0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM },
117 	{ "twi",	0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM },
118 	{ "mulli",	0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM },
119 	{ "subfic",	0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM },
120 	{ "cmplwi",	0xfc200000, 0x28000000, Op_crfD | Op_A | Op_SIMM },
121 	{ "cmpldi",	0xfc200000, 0x28200000, Op_crfD | Op_A | Op_SIMM },
122 	{ "cmpwi",	0xfc200000, 0x2c000000, Op_crfD | Op_A | Op_SIMM },
123 	{ "cmpdi",	0xfc200000, 0x2c200000, Op_crfD | Op_A | Op_SIMM },
124 	{ "addic",	0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM },
125 	{ "addic.",	0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM },
126 	{ "addi",	0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM },
127 	{ "addis",	0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM },
128 	{ "b",		0xfc000000, 0x40000000, Op_BC | Op_BD | Op_AA | Op_LK }, /* bc */
129 	{ "sc",		0xffffffff, 0x44000002, 0 },
130 	{ "b",		0xfc000000, 0x48000000, Op_LI | Op_AA | Op_LK },
132 	{ "rlwimi",	0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc },
133 	{ "rlwinm",	0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc },
134 	{ "rlwnm",	0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc },
136 	{ "ori",	0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM },
137 	{ "oris",	0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM },
138 	{ "xori",	0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM },
139 	{ "xoris",	0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM },
141 	{ "andi.",	0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM },
142 	{ "andis.",	0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM },
144 	{ "lwz",	0xfc000000, 0x80000000, Op_D | Op_dA },
145 	{ "lwzu",	0xfc000000, 0x84000000, Op_D | Op_dA },
146 	{ "lbz",	0xfc000000, 0x88000000, Op_D | Op_dA },
147 	{ "lbzu",	0xfc000000, 0x8c000000, Op_D | Op_dA },
148 	{ "stw",	0xfc000000, 0x90000000, Op_ST | Op_dA },
149 	{ "stwu",	0xfc000000, 0x94000000, Op_ST | Op_dA },
150 	{ "stb",	0xfc000000, 0x98000000, Op_ST | Op_dA },
151 	{ "stbu",	0xfc000000, 0x9c000000, Op_ST | Op_dA },
153 	{ "lhz",	0xfc000000, 0xa0000000, Op_D | Op_dA },
154 	{ "lhzu",	0xfc000000, 0xa4000000, Op_D | Op_dA },
155 	{ "lha",	0xfc000000, 0xa8000000, Op_D | Op_dA },
156 	{ "lhau",	0xfc000000, 0xac000000, Op_D | Op_dA },
157 	{ "sth",	0xfc000000, 0xb0000000, Op_ST | Op_dA },
158 	{ "sthu",	0xfc000000, 0xb4000000, Op_ST | Op_dA },
159 	{ "lmw",	0xfc000000, 0xb8000000, Op_D | Op_dA },
160 	{ "stmw",	0xfc000000, 0xbc000000, Op_ST | Op_dA },
162 	{ "lfs",	0xfc000000, 0xc0000000, Op_D | Op_dA },
163 	{ "lfsu",	0xfc000000, 0xc4000000, Op_D | Op_dA },
164 	{ "lfd",	0xfc000000, 0xc8000000, Op_D | Op_dA },
165 	{ "lfdu",	0xfc000000, 0xcc000000, Op_D | Op_dA },
167 	{ "stfs",	0xfc000000, 0xd0000000, Op_ST | Op_dA },
168 	{ "stfsu",	0xfc000000, 0xd4000000, Op_ST | Op_dA },
169 	{ "stfd",	0xfc000000, 0xd8000000, Op_ST | Op_dA },
170 	{ "stfdu",	0xfc000000, 0xdc000000, Op_ST | Op_dA },
171 	{ "",		0x0,		0x0, 0 }
176 /* 0x13 << 2 */
177 	{ "mcrf",	0xfc0007fe, 0x4c000000, Op_crfD | Op_crfS },
178 	{ "b",		0xfc0007fe, 0x4c000020, Op_BC | Op_LK }, /* bclr */
179 	{ "crnor",	0xfc0007fe, 0x4c000042, Op_crbD | Op_crbA | Op_crbB },
180 	{ "rfi",	0xfc0007fe, 0x4c000064, 0 },
181 	{ "crandc",	0xfc0007fe, 0x4c000102, Op_crbD | Op_crbA | Op_crbB },
182 	{ "isync",	0xfc0007fe, 0x4c00012c, 0 },
183 	{ "crxor",	0xfc0007fe, 0x4c000182, Op_crbD | Op_crbA | Op_crbB },
184 	{ "crnand",	0xfc0007fe, 0x4c0001c2, Op_crbD | Op_crbA | Op_crbB },
185 	{ "crand",	0xfc0007fe, 0x4c000202, Op_crbD | Op_crbA | Op_crbB },
186 	{ "creqv",	0xfc0007fe, 0x4c000242, Op_crbD | Op_crbA | Op_crbB },
187 	{ "crorc",	0xfc0007fe, 0x4c000342, Op_crbD | Op_crbA | Op_crbB },
188 	{ "cror",	0xfc0007fe, 0x4c000382, Op_crbD | Op_crbA | Op_crbB },
189 	{ "b",		0xfc0007fe, 0x4c000420, Op_BC | Op_LK }, /* bcctr */
190 	{ "",		0x0,		0x0, 0 }
195 	{ "rldicl",	0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc },
196 	{ "rldicr",	0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc },
197 	{ "rldic",	0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc },
198 	{ "rldimi",	0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc },
199 	{ "rldcl",	0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc },
200 	{ "rldcr",	0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc },
201 	{ "",		0x0,		0x0, 0 }
207 	{ "cmpw",	0xfc2007fe, 0x7c000000, Op_crfD | Op_A | Op_B },
208 	{ "cmpd",	0xfc2007fe, 0x7c200000, Op_crfD | Op_A | Op_B },
209 	{ "tw",		0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B },
210 	{ "subfc",	0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
211 	{ "mulhdu",	0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc },
212 	{ "addc",	0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
213 	{ "mulhwu",	0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc },
214 	{ "isellt",	0xfc0007ff, 0x7c00001e, Op_D | Op_A | Op_B },
215 	{ "iselgt",	0xfc0007ff, 0x7c00005e, Op_D | Op_A | Op_B },
216 	{ "iseleq",	0xfc0007ff, 0x7c00009e, Op_D | Op_A | Op_B },
218 	{ "mfcr",	0xfc0007fe, 0x7c000026, Op_D },
219 	{ "lwarx",	0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B },
220 	{ "ldx",	0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B },
221 	{ "lwzx",	0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B },
222 	{ "slw",	0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc },
223 	{ "cntlzw",	0xfc0007fe, 0x7c000034, Op_S | Op_A | Op_Rc },
224 	{ "sld",	0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc },
225 	{ "and",	0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc },
226 	{ "cmplw",	0xfc2007fe, 0x7c000040, Op_crfD | Op_A | Op_B },
227 	{ "cmpld",	0xfc2007fe, 0x7c200040, Op_crfD | Op_A | Op_B },
228 	{ "subf",	0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
229 	{ "ldux",	0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B },
230 	{ "dcbst",	0xfc0007fe, 0x7c00006c, Op_A | Op_B },
231 	{ "lwzux",	0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B },
232 	{ "cntlzd",	0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc },
233 	{ "andc",	0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc },
234 	{ "td",		0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B },
235 	{ "mulhd",	0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc },
236 	{ "mulhw",	0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc },
237 	{ "mfmsr",	0xfc0007fe, 0x7c0000a6, Op_D },
238 	{ "ldarx",	0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B },
239 	{ "dcbf",	0xfc0007fe, 0x7c0000ac, Op_A | Op_B },
240 	{ "lbzx",	0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B },
241 	{ "neg",	0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc },
242 	{ "lbzux",	0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B },
243 	{ "nor",	0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc },
244 	{ "wrtee",	0xfc0003ff, 0x7c000106, Op_S },
245 	{ "subfe",	0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
246 	{ "adde",	0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
247 	{ "mtcrf",	0xfc0007fe, 0x7c000120, Op_S | Op_CRM },
248 	{ "mtmsr",	0xfc0007fe, 0x7c000124, Op_S },
249 	{ "stdx",	0xfc0007fe, 0x7c00012a, Op_ST | Op_A | Op_B },
250 	{ "stwcx.",	0xfc0007ff, 0x7c00012d, Op_ST | Op_A | Op_B },
251 	{ "stwx",	0xfc0007fe, 0x7c00012e, Op_ST | Op_A | Op_B },
252 	{ "wrteei",	0xfc0003fe, 0x7c000146, 0 },	/* XXX: out of flags! */
253 	{ "stdux",	0xfc0007fe, 0x7c00016a, Op_ST | Op_A | Op_B },
254 	{ "stwux",	0xfc0007fe, 0x7c00016e, Op_ST | Op_A | Op_B },
255 	{ "subfze",	0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc },
256 	{ "addze",	0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc },
257 	{ "mtsr",	0xfc0007fe, 0x7c0001a4, Op_S | Op_SR },
258 	{ "stdcx.",	0xfc0007ff, 0x7c0001ad, Op_ST | Op_A | Op_B },
259 	{ "stbx",	0xfc0007fe, 0x7c0001ae, Op_ST | Op_A | Op_B },
260 	{ "subfme",	0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc },
261 	{ "mulld",	0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
262 	{ "addme",	0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc },
263 	{ "mullw",	0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
264 	{ "mtsrin",	0xfc0007fe, 0x7c0001e4, Op_S | Op_B },
265 	{ "dcbtst",	0xfc0007fe, 0x7c0001ec, Op_A | Op_B },
266 	{ "stbux",	0xfc0007fe, 0x7c0001ee, Op_ST | Op_A | Op_B },
267 	{ "add",	0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
268 	{ "dcbt",	0xfc0007fe, 0x7c00022c, Op_A | Op_B },
269 	{ "lhzx",	0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B },
270 	{ "eqv",	0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc },
271 	{ "tlbie",	0xfc0007fe, 0x7c000264, Op_B },
272 	{ "eciwx",	0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B },
273 	{ "lhzux",	0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B },
274 	{ "xor",	0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc },
275 	{ "mfdcr",	0xfc0007fe, 0x7c000286, Op_D | Op_dcr },
276 	{ "mfspr",	0xfc0007fe, 0x7c0002a6, Op_D | Op_spr },
277 	{ "lwax",	0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B },
278 	{ "lhax",	0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B },
279 	{ "tlbia",	0xfc0007fe, 0x7c0002e4, 0 },
280 	{ "mftb",	0xfc0007fe, 0x7c0002e6, Op_D | Op_tbr },
281 	{ "lwaux",	0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B },
282 	{ "lhaux",	0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B },
283 	{ "sthx",	0xfc0007fe, 0x7c00032e, Op_ST | Op_A | Op_B },
284 	{ "orc",	0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc },
285 	{ "ecowx",	0xfc0007fe, 0x7c00036c, Op_ST | Op_A | Op_B | Op_Rc },
286 	{ "slbie",	0xfc0007fc, 0x7c000364, Op_B },
287 	{ "sthux",	0xfc0007fe, 0x7c00036e, Op_ST | Op_A | Op_B },
288 	{ "or",		0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc },
289 	{ "mtdcr",	0xfc0007fe, 0x7c000386, Op_S | Op_dcr },
290 	{ "divdu",	0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
291 	{ "divwu",	0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
292 	{ "mtspr",	0xfc0007fe, 0x7c0003a6, Op_S | Op_spr },
293 	{ "dcbi",	0xfc0007fe, 0x7c0003ac, Op_A | Op_B },
294 	{ "nand",	0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc },
295 	{ "dcread",	0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B },
296 	{ "divd",	0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc },
297 	{ "divw",	0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc },
298 	{ "slbia",	0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc },
299 	{ "mcrxr",	0xfc0007fe, 0x7c000400, Op_crfD },
300 	{ "lswx",	0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B },
301 	{ "lwbrx",	0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B },
302 	{ "lfsx",	0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B },
303 	{ "srw",	0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc },
304 	{ "srd",	0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc },
305 	{ "tlbsync",	0xfc0007fe, 0x7c00046c, 0 },
306 	{ "lfsux",	0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B },
307 	{ "mfsr",	0xfc0007fe, 0x7c0004a6, Op_D | Op_SR },
308 	{ "lswi",	0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB },
309 	{ "sync",	0xfc6007fe, 0x7c0004ac, 0 },
310 	{ "lwsync",	0xfc6007fe, 0x7c2004ac, 0 },
311 	{ "ptesync",	0xfc6007fe, 0x7c4004ac, 0 },
312 	{ "lfdx",	0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B },
313 	{ "lfdux",	0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B },
314 	{ "mfsrin",	0xfc0007fe, 0x7c000526, Op_D | Op_B },
315 	{ "stswx",	0xfc0007fe, 0x7c00052a, Op_ST | Op_A | Op_B },
316 	{ "stwbrx",	0xfc0007fe, 0x7c00052c, Op_ST | Op_A | Op_B },
317 	{ "stfsx",	0xfc0007fe, 0x7c00052e, Op_ST | Op_A | Op_B },
318 	{ "stfsux",	0xfc0007fe, 0x7c00056e, Op_ST | Op_A | Op_B },
319 	{ "stswi",	0xfc0007fe, 0x7c0005aa, Op_ST | Op_A | Op_NB },
320 	{ "stfdx",	0xfc0007fe, 0x7c0005ae, Op_ST | Op_A | Op_B },
321 	{ "stfdux",	0xfc0007fe, 0x7c0005ee, Op_ST | Op_A | Op_B },
322 	{ "lhbrx",	0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B },
323 	{ "sraw",	0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B },
324 	{ "srad",	0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc },
325 	{ "srawi",	0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_rSH | Op_Rc },
326 	{ "sradi",	0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh },
327 	{ "eieio",	0xfc0007fe, 0x7c0006ac, 0 },
328 	{ "tlbsx",	0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc },
329 	{ "sthbrx",	0xfc0007fe, 0x7c00072c, Op_ST | Op_A | Op_B },
330 	{ "extsh",	0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_Rc },
331 	{ "tlbre",	0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS },
332 	{ "extsb",	0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc },
333 	{ "icbi",	0xfc0007fe, 0x7c0007ac, Op_A | Op_B },
334 	{ "tlbwe",	0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS },
335 	{ "stfiwx",	0xfc0007fe, 0x7c0007ae, Op_ST | Op_A | Op_B },
336 	{ "extsw",	0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc },
337 	{ "dcbz",	0xfc0007fe, 0x7c0007ec, Op_A | Op_B },
338 	{ "",		0x0,		0x0, 0 }
343 	{ "ld",		0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds },
344 	{ "ldu",	0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds },
345 	{ "lwa",	0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds },
346 	{ "",		0x0,		0x0, 0 }
350 	{ "fdivs",	0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc },
351 	{ "fsubs",	0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc },
353 	{ "fadds",	0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc },
354 	{ "fsqrts",	0xfc00003e, 0xec00002c, Op_D | Op_B | Op_Rc },
355 	{ "fres",	0xfc00003e, 0xec000030, Op_D | Op_B | Op_Rc },
356 	{ "fmuls",	0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc },
357 	{ "fmsubs",	0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc },
358 	{ "fmadds",	0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc },
359 	{ "fnmsubs",	0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc },
360 	{ "fnmadds",	0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc },
361 	{ "",		0x0,		0x0, 0 }
365 	{ "std",	0xfc000003, 0xf8000000, Op_ST | Op_A | Op_ds },
366 	{ "stdu",	0xfc000003, 0xf8000001, Op_ST | Op_A | Op_ds },
367 	{ "",		0x0,		0x0, 0 }
372 	{ "fcmpu",	0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B },
373 	{ "frsp",	0xfc0007fe, 0xfc000018, Op_D | Op_B | Op_Rc },
374 	{ "fctiw",	0xfc0007fe, 0xfc00001c, Op_D | Op_B | Op_Rc },
375 	{ "fctiwz",	0xfc0007fe, 0xfc00001e, Op_D | Op_B | Op_Rc },
377 	{ "fdiv",	0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc },
378 	{ "fsub",	0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc },
379 	{ "fadd",	0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc },
380 	{ "fsqrt",	0xfc00003e, 0xfc00002c, Op_D | Op_B | Op_Rc },
381 	{ "fsel",	0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc },
382 	{ "fmul",	0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc },
383 	{ "frsqrte",	0xfc00003e, 0xfc000034, Op_D | Op_B | Op_Rc },
384 	{ "fmsub",	0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc },
385 	{ "fmadd",	0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc },
386 	{ "fnmsub",	0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc },
387 	{ "fnmadd",	0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc },
389 	{ "fcmpo",	0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B },
390 	{ "mtfsb1",	0xfc0007fe, 0xfc00004c, Op_crfD | Op_Rc },
391 	{ "fneg",	0xfc0007fe, 0xfc000050, Op_D | Op_B | Op_Rc },
392 	{ "mcrfs",	0xfc0007fe, 0xfc000080, Op_D | Op_B | Op_Rc },
393 	{ "mtfsb0",	0xfc0007fe, 0xfc00008c, Op_crfD | Op_Rc },
394 	{ "fmr",	0xfc0007fe, 0xfc000090, Op_D | Op_B | Op_Rc },
395 	{ "mtfsfi",	0xfc0007fe, 0xfc00010c, 0 },	/* XXX: out of flags! */
397 	{ "fnabs",	0xfc0007fe, 0xfc000110, Op_D | Op_B | Op_Rc },
398 	{ "fabs",	0xfc0007fe, 0xfc000210, Op_D | Op_B | Op_Rc },
399 	{ "mffs",	0xfc0007fe, 0xfc00048e, Op_D | Op_B | Op_Rc },
400 	{ "mtfsf",	0xfc0007fe, 0xfc00058e, Op_FM | Op_B | Op_Rc },
401 	{ "fctid",	0xfc0007fe, 0xfc00065c, Op_D | Op_B | Op_Rc },
402 	{ "fctidz",	0xfc0007fe, 0xfc00065e, Op_D | Op_B | Op_Rc },
403 	{ "fcfid",	0xfc0007fe, 0xfc00069c, Op_D | Op_B | Op_Rc },
404 	{ "",		0x0,		0x0, 0 }
413 	{ 0x000, "mq" },
414 	{ 0x001, "xer" },
415 	{ 0x008, "lr" },
416 	{ 0x009, "ctr" },
417 	{ 0x012, "dsisr" },
418 	{ 0x013, "dar" },
419 	{ 0x016, "dec" },
420 	{ 0x019, "sdr1" },
421 	{ 0x01a, "srr0" },
422 	{ 0x01b, "srr1" },
423 	{ 0x100, "vrsave" },
424 	{ 0x110, "sprg0" },
425 	{ 0x111, "sprg1" },
426 	{ 0x112, "sprg2" },
427 	{ 0x113, "sprg3" },
428 	{ 0x114, "sprg4" },
429 	{ 0x115, "sprg5" },
430 	{ 0x116, "sprg6" },
431 	{ 0x117, "sprg7" },
432 	{ 0x118, "asr" },
433 	{ 0x11a, "aer" },
434 	{ 0x11c, "tbl" },
435 	{ 0x11d, "tbu" },
436 	{ 0x11f, "pvr" },
437 	{ 0x210, "ibat0u" },
438 	{ 0x211, "ibat0l" },
439 	{ 0x212, "ibat1u" },
440 	{ 0x213, "ibat1l" },
441 	{ 0x214, "ibat2u" },
442 	{ 0x215, "ibat2l" },
443 	{ 0x216, "ibat3u" },
444 	{ 0x217, "ibat3l" },
445 	{ 0x218, "dbat0u" },
446 	{ 0x219, "dbat0l" },
447 	{ 0x21a, "dbat1u" },
448 	{ 0x21b, "dbat1l" },
449 	{ 0x21c, "dbat2u" },
450 	{ 0x21d, "dbat2l" },
451 	{ 0x21e, "dbat3u" },
452 	{ 0x21f, "dbat3l" },
453 	{ 0x230, "ibat4u" },
454 	{ 0x231, "ibat4l" },
455 	{ 0x232, "ibat5u" },
456 	{ 0x233, "ibat5l" },
457 	{ 0x234, "ibat6u" },
458 	{ 0x235, "ibat6l" },
459 	{ 0x236, "ibat7u" },
460 	{ 0x237, "ibat7l" },
461 	{ 0x238, "dbat4u" },
462 	{ 0x239, "dbat4l" },
463 	{ 0x23a, "dbat5u" },
464 	{ 0x23b, "dbat5l" },
465 	{ 0x23c, "dbat6u" },
466 	{ 0x23d, "dbat6l" },
467 	{ 0x23e, "dbat7u" },
468 	{ 0x23f, "dbat7l" },
469 	{ 0x3b0, "zpr" },
470 	{ 0x3b1, "pid" },
471 	{ 0x3b3, "ccr0" },
472 	{ 0x3b4, "iac3" },
473 	{ 0x3b5, "iac4" },
474 	{ 0x3b6, "dvc1" },
475 	{ 0x3b7, "dvc2" },
476 	{ 0x3b9, "sgr" },
477 	{ 0x3ba, "dcwr" },
478 	{ 0x3bb, "sler" },
479 	{ 0x3bc, "su0r" },
480 	{ 0x3bd, "dbcr1" },
481 	{ 0x3d3, "icdbdr" },
482 	{ 0x3d4, "esr" },
483 	{ 0x3d5, "dear" },
484 	{ 0x3d6, "evpr" },
485 	{ 0x3d8, "tsr" },
486 	{ 0x3da, "tcr" },
487 	{ 0x3db, "pit" },
488 	{ 0x3de, "srr2" },
489 	{ 0x3df, "srr3" },
490 	{ 0x3f0, "hid0" },
491 	{ 0x3f1, "hid1" },
492 	{ 0x3f2, "iabr" },
493 	{ 0x3f3, "hid2" },
494 	{ 0x3f5, "dabr" },
495 	{ 0x3f6, "msscr0" },
496 	{ 0x3f7, "msscr1" },
497 	{ 0x3f9, "l2cr" },
498 	{ 0x3fa, "dccr" },
499 	{ 0x3fb, "iccr" },
500 	{ 0x3ff, "pir" },
501 	{ 0, NULL }
505 	{ 0x010, "sdram0_cfgaddr" },
506 	{ 0x011, "sdram0_cfgdata" },
507 	{ 0x012, "ebc0_cfgaddr" },
508 	{ 0x013, "ebc0_cfgdata" },
509 	{ 0x014, "dcp0_cfgaddr" },
510 	{ 0x015, "dcp0_cfgdata" },
511 	{ 0x018, "ocm0_isarc" },
512 	{ 0x019, "ocm0_iscntl" },
513 	{ 0x01a, "ocm0_dsarc" },
514 	{ 0x01b, "ocm0_dscntl" },
515 	{ 0x084, "plb0_besr" },
516 	{ 0x086, "plb0_bear" },
517 	{ 0x087, "plb0_acr" },
518 	{ 0x0a0, "pob0_besr0" },
519 	{ 0x0a2, "pob0_bear" },
520 	{ 0x0a4, "pob0_besr1" },
521 	{ 0x0b0, "cpc0_pllmr" },
522 	{ 0x0b1, "cpc0_cr0" },
523 	{ 0x0b2, "cpc0_cr1" },
524 	{ 0x0b4, "cpc0_psr" },
525 	{ 0x0b5, "cpc0_jtagid" },
526 	{ 0x0b8, "cpc0_sr" },
527 	{ 0x0b9, "cpc0_er" },
528 	{ 0x0ba, "cpc0_fr" },
529 	{ 0x0c0, "uic0_sr" },
530 	{ 0x0c2, "uic0_er" },
531 	{ 0x0c3, "uic0_cr" },
532 	{ 0x0c4, "uic0_pr" },
533 	{ 0x0c5, "uic0_tr" },
534 	{ 0x0c6, "uic0_msr" },
535 	{ 0x0c7, "uic0_vr" },
536 	{ 0x0c8, "uic0_vcr" },
537 	{ 0x100, "dma0_cr0" },
538 	{ 0x101, "dma0_ct0" },
539 	{ 0x102, "dma0_da0" },
540 	{ 0x103, "dma0_sa0" },
541 	{ 0x104, "dma0_sg0" },
542 	{ 0x108, "dma0_cr1" },
543 	{ 0x109, "dma0_ct1" },
544 	{ 0x10a, "dma0_da1" },
545 	{ 0x10b, "dma0_sa1" },
546 	{ 0x10c, "dma0_sg1" },
547 	{ 0x110, "dma0_cr2" },
548 	{ 0x111, "dma0_ct2" },
549 	{ 0x112, "dma0_da2" },
550 	{ 0x113, "dma0_sa2" },
551 	{ 0x114, "dma0_sg2" },
552 	{ 0x118, "dma0_cr3" },
553 	{ 0x119, "dma0_ct3" },
554 	{ 0x11a, "dma0_da3" },
555 	{ 0x11b, "dma0_sa3" },
556 	{ 0x11c, "dma0_sg3" },
557 	{ 0x120, "dma0_sr" },
558 	{ 0x123, "dma0_sgc" },
559 	{ 0x125, "dma0_slp" },
560 	{ 0x126, "dma0_pol" },
561 	{ 0x180, "mal0_cfg" },
562 	{ 0x181, "mal0_esr" },
563 	{ 0x182, "mal0_ier" },
564 	{ 0x184, "mal0_txcasr" },
565 	{ 0x185, "mal0_txcarr" },
566 	{ 0x186, "mal0_txeobisr" },
567 	{ 0x187, "mal0_txdeir" },
568 	{ 0x190, "mal0_rxcasr" },
569 	{ 0x191, "mal0_rxcarr" },
570 	{ 0x192, "mal0_rxeobisr" },
571 	{ 0x193, "mal0_rxdeir" },
572 	{ 0x1a0, "mal0_txctp0r" },
573 	{ 0x1a1, "mal0_txctp1r" },
574 	{ 0x1a2, "mal0_txctp2r" },
575 	{ 0x1a3, "mal0_txctp3r" },
576 	{ 0x1c0, "mal0_rxctp0r" },
577 	{ 0x1e0, "mal0_rcbs0" },
578 	{ 0, NULL }
612 	} while(0)  in disasm_fields()
627 				if (popcode->code == 0x40000000) {  in disasm_fields()
644 			if ((BO & 24) == 0)  in disasm_fields()
651 		if (popcode->code == 0x4c000020)  in disasm_fields()
653 		else if (popcode->code == 0x4c000420)  in disasm_fields()
655 		if ((BO & 20) != 20 && (func & Op_BO) == 0)  in disasm_fields()
668 		if (instr & 0x1)  in disasm_fields()
672 		if (instr & 0x1)  in disasm_fields()
674 		if (instr & 0x2) {  in disasm_fields()
676 			loc = 0; /* Absolute address */  in disasm_fields()
680 		if (instr & 0x1)  in disasm_fields()
688 		y = (instr & 0x200000) != 0;  in disasm_fields()
689 		if (popcode->code == 0x40000000) {  in disasm_fields()
704 	if (strcmp(popcode->name, "wrteei") == 0) {  in disasm_fields()
710 	else if (strcmp(popcode->name, "mtfsfi") == 0) {  in disasm_fields()
715 		APP_PSTR("0x%x", UI);  in disasm_fields()
722 		APP_PSTR("0x%x, ", FM);  in disasm_fields()
758 		APP_PSTR("0x%x, ", CRM);  in disasm_fields()
776 		if (A & 0x8000) {  in disasm_fields()
778 			A = 0x10000-A;  in disasm_fields()
780 		APP_PSTR("0x%x", A);  in disasm_fields()
800 		for (i = 0; regs[i].name != NULL; i++)  in disasm_fields()
862 		APP_PSTR("0x%x", LI);  in disasm_fields()
869 		if (IMM & 0x8000) {  in disasm_fields()
871 			IMM = 0x10000-IMM;  in disasm_fields()
880 		APP_PSTR("0x%x", IMM);  in disasm_fields()
892 		APP_PSTR("0x%x", BD);  in disasm_fields()
898 		APP_PSTR("0x%x", ds);  in disasm_fields()
906 		APP_PSTR(", 0x%x", me);  in disasm_fields()
971 		if (NB == 0)  in disasm_fields()
1033 	int found = 0;  in dis_ppc()
1037 	for (i = 0, op = &opcodeset[0];  in dis_ppc()
1038 	    found == 0 && op->mask != 0;  in dis_ppc()