Lines Matching +full:bank +full:- +full:width
1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2006-2008, Juniper Networks, Inc.
133 * of 32KB - 4GB. Otherwise error code is returned. Value representing
153 return (0xffff8000 << (n - 15));
163 if (sc->sc_range[r].size == 0)
166 pmap_unmapdev((void *)sc->sc_range[r].kva,
167 sc->sc_range[r].size);
168 law_disable(OCP85XX_TGTIF_LBC, sc->sc_range[r].addr,
169 sc->sc_range[r].size);
182 bzero(sc->sc_range, sizeof(sc->sc_range));
189 size = sc->sc_banks[i].size;
193 start = sc->sc_banks[i].addr;
195 /* Avoid wrap-around bugs. */
196 end = sc->sc_range[r].addr - 1 + sc->sc_range[r].size;
197 if (start > 0 && end == start - 1) {
198 sc->sc_range[r].size += size;
201 /* Avoid wrap-around bugs. */
202 end = start - 1 + size;
203 if (sc->sc_range[r].addr > 0 &&
204 end == sc->sc_range[r].addr - 1) {
205 sc->sc_range[r].addr = start;
206 sc->sc_range[r].size += size;
213 while (r < ranges && sc->sc_range[r].addr < start)
215 for (s = ranges; s > r; s--)
216 sc->sc_range[s] = sc->sc_range[s-1];
217 sc->sc_range[r].addr = start;
218 sc->sc_range[r].size = size;
228 while (r < ranges - 1) {
229 end = sc->sc_range[r].addr + sc->sc_range[r].size;
230 if (end != sc->sc_range[r+1].addr) {
234 sc->sc_range[r].size += sc->sc_range[r+1].size;
235 for (s = r + 1; s < ranges - 1; s++)
236 sc->sc_range[s] = sc->sc_range[s+1];
237 bzero(&sc->sc_range[s], sizeof(sc->sc_range[s]));
238 ranges--;
246 start = sc->sc_range[r].addr;
247 size = sc->sc_range[r].size;
251 sc->sc_range[r].kva = (vm_offset_t)pmap_mapdev(start, size);
260 size = sc->sc_banks[i].size;
264 start = sc->sc_banks[i].addr;
266 end = sc->sc_range[r].addr - 1 + sc->sc_range[r].size;
267 if (start >= sc->sc_range[r].addr &&
268 start - 1 + size <= end)
272 sc->sc_banks[i].kva = sc->sc_range[r].kva +
273 (start - sc->sc_range[r].addr);
288 size = sc->sc_banks[i].size;
295 regval = sc->sc_banks[i].addr;
296 switch (sc->sc_banks[i].width) {
310 regval |= (sc->sc_banks[i].decc << 9);
311 regval |= (sc->sc_banks[i].wp << 8);
312 regval |= (sc->sc_banks[i].msel << 5);
313 regval |= (sc->sc_banks[i].atom << 2);
315 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
322 switch (sc->sc_banks[i].msel) {
338 bus_space_write_4(sc->sc_bst, sc->sc_bsh,
352 pcell_t width;
353 int bank;
355 if (OF_getprop(node, "bank-width", (void *)&width, sizeof(width)) <= 0)
358 bank = di->di_bank;
359 if (sc->sc_banks[bank].size == 0)
362 /* Express width in bits. */
363 sc->sc_banks[bank].width = width * 8;
374 int i, j, rv, bank;
390 bank = fdt_data_get((void *)reg, 1);
391 di->di_bank = bank;
396 for (j = 0; j < addr_cells - 1; j++) {
402 count |= reg[addr_cells + j - 1];
404 reg += addr_cells - 1 + size_cells;
407 start = sc->sc_banks[bank].kva + start;
408 end = start + count - 1;
410 debugf("reg addr bank = %d, start = %jx, end = %jx, "
411 "count = %jx\n", bank, start, end, count);
413 /* Use bank (CS) cell as rid. */
414 resource_list_add(&di->di_res, SYS_RES_MEMORY, bank, start,
428 ltesr = bus_space_read_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LTESR);
429 sc->sc_ltesr = ltesr;
430 bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LTESR, ltesr);
431 wakeup(sc->sc_dev);
459 int bank, error, i, j;
462 sc->sc_dev = dev;
464 sc->sc_mrid = 0;
465 sc->sc_mres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_mrid,
467 if (sc->sc_mres == NULL)
470 sc->sc_bst = rman_get_bustag(sc->sc_mres);
471 sc->sc_bsh = rman_get_bushandle(sc->sc_mres);
473 for (bank = 0; bank < LBC_DEV_MAX; bank++) {
474 bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_BR(bank), 0);
475 bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_OR(bank), 0);
480 * - enable Local Bus
481 * - set data buffer control signal function
482 * - disable parity byte select
483 * - set ECC parity type
484 * - set bus monitor timing and timer prescale
486 bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LBCR, 0);
490 * - disable PLL bypass mode
491 * - configure LCLK delay cycles for the assertion of LALE
492 * - set system clock divider
494 bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LCRR, 0x00030008);
496 bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LTEDR, 0);
497 bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LTESR, ~0);
498 bus_space_write_4(sc->sc_bst, sc->sc_bsh, LBC85XX_LTEIR, 0x64080001);
500 sc->sc_irid = 0;
501 sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_irid,
503 if (sc->sc_ires != NULL) {
504 error = bus_setup_intr(dev, sc->sc_ires,
506 &sc->sc_icookie);
509 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irid,
510 sc->sc_ires);
511 sc->sc_ires = NULL;
515 sc->sc_ltesr = ~0;
519 rm = &sc->sc_rman;
520 rm->rm_type = RMAN_ARRAY;
521 rm->rm_descr = "Local Bus Space";
526 error = rman_manage_region(rm, rm->rm_start, rm->rm_end);
536 if ((fdt_addrsize_cells(node, &sc->sc_addr_cells,
537 &sc->sc_size_cells)) != 0) {
544 device_printf(dev, "unsupported parent #addr-cells\n");
548 tuple_size = sizeof(pcell_t) * (sc->sc_addr_cells + par_addr_cells +
549 sc->sc_size_cells);
562 sc->sc_addr_cells, sc->sc_size_cells, tuple_size, tuples);
567 /* The first cell is the bank (chip select) number. */
568 bank = fdt_data_get(ranges, 1);
569 if (bank < 0 || bank > LBC_DEV_MAX) {
570 device_printf(dev, "bank out of range: %d\n", bank);
581 for (j = 0; j < sc->sc_addr_cells - 1; j++) {
587 /* Parent bus start address of this bank. */
595 size = fdt_data_get((void *)ranges, sc->sc_size_cells);
596 ranges += sc->sc_size_cells;
597 debugf("bank = %d, start = %jx, size = %jx\n", bank,
600 sc->sc_banks[bank].addr = start + offset;
601 sc->sc_banks[bank].size = size;
604 * Attributes for the bank.
609 sc->sc_banks[bank].width = 16;
610 sc->sc_banks[bank].msel = LBCRES_MSEL_GPCM;
611 sc->sc_banks[bank].decc = LBCRES_DECC_DISABLED;
612 sc->sc_banks[bank].atom = LBCRES_ATOM_DISABLED;
613 sc->sc_banks[bank].wp = 0;
617 * Initialize mem-mappings for the LBC banks (i.e. chip selects).
629 if (ofw_bus_gen_setup_devinfo(&di->di_ofw, child) != 0) {
635 resource_list_init(&di->di_res);
640 ofw_bus_gen_destroy_devinfo(&di->di_ofw);
651 di->di_ofw.obd_name);
652 resource_list_free(&di->di_res);
653 ofw_bus_gen_destroy_devinfo(&di->di_ofw);
657 debugf("added child name='%s', node=%x\n", di->di_ofw.obd_name,
673 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mrid, sc->sc_mres);
693 return (&sc->sc_rman);
728 rid = &di->di_bank;
730 rle = resource_list_find(&di->di_res, type, *rid);
736 start = rle->start;
737 count = rle->count;
738 end = start + count - 1;
752 rl = &di->di_res;
843 map->r_bustag = &bs_be_tag;
844 map->r_bushandle = start;
845 map->r_size = length;
846 map->r_vaddr = NULL;
872 return (&di->di_ofw);
891 if (off == LBC85XX_LTESR && sc->sc_ltesr != ~0u) {
892 sc->sc_ltesr ^= (val & sc->sc_ltesr);
897 sc->sc_ltesr = ~0u;
898 bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
918 if (off == LBC85XX_LTESR && sc->sc_ltesr != ~0U)
919 val = sc->sc_ltesr;
921 val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);