Lines Matching +full:five +full:- +full:cell
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
43 /* The following routines allow manipulation of the full 64-bit width
88 * architectures the SPR is valid on - 4 for 4xx series,
95 #define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */
96 #define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */
101 #define DSISR_DIRECT 0x80000000 /* Direct-store error exception */
104 #define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */
111 #define DSISR_MC_DERAT_MULTIHIT 0x00000800 /* D-ERAT multi-hit */
112 #define DSISR_MC_TLB_MULTIHIT 0x00000400 /* TLB multi-hit */
115 #define DSISR_MC_SLB_MULTIHIT 0x00000080 /* SLB Multi-hit detected (D-side) */
119 #define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */
120 #define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */
126 #define SRR1_ISI_NOEXECUTE 0x10000000 /* Memory marked no-execute */
151 #define FSCR_IC_EBB 0x0700000000000000ULL /* Access to Event-Based Branch */
153 #define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */
161 #define FSCR_EBB 0x0000000000000080 /* Event-based branch available */
297 #define LPCR_ILE (1ULL << 25) /* Interrupt Little-Endian (ISA 2.07) */
408 #define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */
415 #define SPR_MMCR0_FC56 0x00000010 /* Freeze Counters 5-6 */
430 #define SPR_MMCR1_P8_PMCNSEL_MASK(n) (0xffUL << ((3-(n))*8))
431 #define SPR_MMCR1_P8_PMCNSEL(n, v) ((unsigned long)(v) << ((3-(n))*8))
434 #define SPR_MMCR2_CNBIT(n, bit) ((bit) << (((5 - (n)) * 9) + 10))
448 #define M_TWB_L1TB 0xfffff000 /* level-1 translation base */
449 #define M_TWB_L1INDX 0x00000ffc /* level-1 index */
454 #define SPR_BESCRSU 0x321 /* .6. Branch Event Status and Control Set Register (upper 32-bit) */
456 #define SPR_BESCRRU 0x323 /* .6. Branch Event Status and Control Register (upper 32-bit) */
457 #define SPR_EBBHR 0x324 /* .6. Event-based Branch Handler Register */
458 #define SPR_EBBRR 0x325 /* .6. Event-based Branch Return Register */
555 #define SPR_CELL_TSRL 0x380 /* ... Cell BE Thread Status Register */
556 #define SPR_CELL_TSCR 0x399 /* ... Cell BE Thread Switch Register */
577 #define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */
581 #define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */
583 #define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */
584 #define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */
590 #define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */
592 #define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */
593 #define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/
596 #define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */
597 #define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */
598 #define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */
599 #define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetch enable */
613 #define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */
618 #define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */
625 #define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */
629 #define L2CR_L2DO 0x00400000 /* 9: L2 data-only.
633 #define L2CR_L2IO_7450 0x00010000 /* 11: L2 instruction-only (MPC745x). */
636 L2ZZ (low-power mode) signal. */
637 #define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */
639 #define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */
640 #define L2CR_L2DO_7450 0x00010000 /* 15: L2 data-only (MPC745x). */
646 #define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */
685 #define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */
688 #define TBR_TBL 0x10c /* 468 Time Base Lower - read */
689 #define TBR_TBU 0x10d /* 468 Time Base Upper - read */
690 #define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */
691 #define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */
696 /* The first five countable [non-]events are common to many PMC's */
714 #define MCSR_NMI 0x00100000 /* Non-maskable interrupt */
725 #define ESR_PIL 0x08000000 /* Program interrupt - illegal */
726 #define ESR_PPR 0x04000000 /* Program interrupt - privileged */
727 #define ESR_PTR 0x02000000 /* Program interrupt - trap */
818 #define SPR_MAS0 0x270 /* ..8 MMU Assist Register 0 Book-E/e500 */
819 #define SPR_MAS1 0x271 /* ..8 MMU Assist Register 1 Book-E/e500 */
820 #define SPR_MAS2 0x272 /* ..8 MMU Assist Register 2 Book-E/e500 */
821 #define SPR_MAS3 0x273 /* ..8 MMU Assist Register 3 Book-E/e500 */
822 #define SPR_MAS4 0x274 /* ..8 MMU Assist Register 4 Book-E/e500 */
823 #define SPR_MAS5 0x275 /* ..8 MMU Assist Register 5 Book-E */
824 #define SPR_MAS6 0x276 /* ..8 MMU Assist Register 6 Book-E/e500 */
825 #define SPR_MAS7 0x3B0 /* ..8 MMU Assist Register 7 Book-E/e500 */
826 #define SPR_MAS8 0x155 /* ..8 MMU Assist Register 8 Book-E/e500 */
834 #define DCR_L2DCDCRAI 0x0000 /* L2 D-Cache DCR Address Pointer */
835 #define DCR_L2DCDCRDI 0x0001 /* L2 D-Cache DCR Data Indirect */