Lines Matching +full:bl +full:- +full:data +full:- +full:offset
1 /*-
2 * Copyright (C) 2007-2009 Semihalf, Rafal Jaworowski <raj@semihalf.com>
20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
107 * - System memory starts from physical address 0
108 * - It's mapped by a single TLB1 entry
109 * - TLB1 mapping is 1:1 pa to va
110 * - Kernel is loaded at 64MB boundary
111 * - All PID registers are set to the same value
112 * - CPU is running in AS=0
119 * - Find TLB1 entry we started in
120 * - Make sure it's protected, invalidate other entries
121 * - Create temp entry in the second AS (make sure it's not TLB[1])
122 * - Switch to temp mapping
123 * - Map 64MB of RAM in TLB1[1]
124 * - Use AS=0, set EPN to VM_MIN_KERNEL_ADDRESS and RPN to kernel load address
125 * - Switch to TLB1[1] mapping
126 * - Invalidate temp mapping
131 * r3-r27 : scratch registers
134 * r30-r31 : arguments (metadata pointer)
199 bl tlb_inval_all
207 bl 1f
209 bl tlb1_find_current /* the entry found is returned in r29 */
211 bl tlb1_inval_all_but_current
216 bl tlb1_temp_mapping_as1
220 bl 2f
222 addi %r4, %r4, (3f - 2b)
232 bl tlb1_inval_entry
255 bl 3f
269 bl 4f
275 rlwinm %r4, %r4, 0, 6, 31 /* Current offset from kernel load address */
279 addi %r4, %r4, (5f - 4b)
293 bl tlb1_inval_entry
302 bl 1f
303 .llong __tocbase + 0x8000 - .
310 /* Get load offset */
311 ld %r31,-0x8000(%r2) /* First TOC entry is TOC base */
315 bl 1f
316 .llong tmpstack + TMPSTACKSZ - 96 - .
323 bl 1f
324 .llong _DYNAMIC-.
333 bl 1f
334 .long tmpstack-.
338 addi %r1, %r1, (TMPSTACKSZ - 16)
343 bl 1f
344 .long _DYNAMIC-.
345 .long _GLOBAL_OFFSET_TABLE_-.
354 bl CNAME(elf_reloc_self)
360 bl CNAME(ivor_setup)
370 bl CNAME(booke_init)
379 bl CNAME(mi_startup)
397 * platform-dependent registers.
399 * Alternatively, this page may be executed using an ePAPR-standardized
400 * method -- writing to the address specified in "cpu-release-addr".
434 nop /* PPC64 alignment word. 64-bit target. */
436 bl 1f /* 32-bit target. */
485 bl tlb_inval_all
490 bl 2f
492 bl tlb1_find_current /* the entry number found is in r29 */
494 bl tlb1_inval_all_but_current
500 bl tlb1_temp_mapping_as1
505 oris %r3, %r3, PSL_CM@h /* Ensure we're in 64-bit after RFI */
507 bl 3f
509 addi %r4, %r4, (4f - 3b)
519 bl tlb1_inval_entry
550 lwz %r4, (bp_kernload - __boot_page + 4)(%r3)
551 LOAD %r5, (bp_virtaddr - __boot_page)(%r3)
557 lwz %r4, (bp_kernload - __boot_page)(%r3)
565 bl 6f
567 rlwinm %r3, %r3, 0, 0xfff /* Offset from boot page start */
569 addi %r3, %r3, (7f - 6b) /* And figure out return address. */
590 bl tlb1_inval_entry
597 bl 1f
598 .llong __tocbase + 0x8000 - .
607 addi %r1,%r1,TMPSTACKSZ-96
612 bl 1f
613 .long tmpstack-.
618 addi %r1, %r1, (TMPSTACKSZ - 16)
624 bl CNAME(ivor_setup)
630 bl 1f
631 .long ap_pcpu-.
638 bl CNAME(pmap_bootstrap_ap)
641 bl CNAME(cpudep_ap_bootstrap)
646 bl CNAME(machdep_ap_bootstrap)
683 rlwinm %r29, %r17, 16, 26, 31 /* MAS0[ESEL] -> r29 */
699 * r4-r5 scratched
718 * r3-r5 scratched
762 * r3-r5 scratched
806 .space 4092 - (__boot_page_padding - __boot_page)
824 /* Invalidate d-cache */
838 /* Disable d-cache */
851 /* Enable d-cache */
863 /* Invalidate i-cache */
876 /* Disable i-cache */
888 /* Enable i-cache */
951 /* Data section */
953 .data